Xpedion Design Systems and Cadence Team on 3G Design

Electronic News, August 21, 2000 by Gale Morrison

Santa Clara, Calif.-based Xpedion Design Systems Inc. and Cadence Design Systems Inc., San Jose, are going to integrate the Xpedion GoldenGate family of RF simulation and modeling products with the Cadence Signal Processing Worksystem (SPW) and Cadence Analog Design Environment.

The main goal of the collaboration is to bring to market software for designing wireless systems, and 3G phones in particular. Xpedion has already integrated its products with the Cossap suite from Synopsys Inc., which competes with SPW.

The integration gets parametric models into the SPW and analog design environment, said Les Wilson, director of marketing at Cadence. Xpedion's GoldenGate/Neural Network Model Compiler (NN-Model Compiler) accepts input data from the Cadence environment or from lab-measured data and generates fully parametric SPW simulation models. The work will particularly benefit the RF IC design community, said Ed Lechner, director of product marketing for analog, mixed signal and RF solutions at Cadence.

The SPW-GoldenGate interface from Xpedion is available now and is included with the purchase of the Xpedion GoldenGate/NN-Model Compiler product. The NN-Model Compiler works in conjunction with the SPW IP Block Wizard, version 4.5 or later, and is priced at $75,000 U.S. list on Unix and Windows platforms. GoldenGate/Sim version 2.0 is available now for use with the Cadence analog environment and is priced at $55,000 U.S. list for Unix platforms and between $10,000 and $40,000 for Windows platforms. Time-based licensing and perpetual licensing are available for both product families.

Synopsys, TSMC Spinning Arcadia Files

Synopsys Inc., Mountain View, Calif., and Taiwan Semiconductor Manufacturing Co. (TSMC), Hsinchu, Taiwan, are jointly developing silicon-calibrated technology files across TSMC's advanced processes including 0.13-micron, for Synopsys' Arcadia layout parasitic extraction tool.

Arcadia technology files for the most-utilized TSMC processes have been certified and are available for download from TSMC's password-controlled Web site.

"Arcadia's accurate parasitic extraction is the foundation for effective power, timing and reliability analysis," said Antun Domic, vice president and general manager of Synopsys' Nanometer Analysis and Test Group. The analysis business is looking to steal some thunder from competitors such as SimplexSolutions Inc. and Ultima Interconnect Technology Inc., and especially from Avant! Corp. and its Star-RC XT line.

Under this agreement, Synopsys and TSMC will jointly develop test chips as well as the silicon-calibrated Arcadia technology files. Synopsys says the use of the Arcadia technology files will allow TSMC customers to gain full-chip verification prior to committing to final design tape-out.