Faster I/Os Spur Analog Design

Electronic News, August 20, 2001 by Gale Morrison

NurLogic finds fertile ground for mixed signal IP; Cadence Design sees AMS language pick-up

RESEARCH TRIANGLE PARK, N.C. -- The battle for supremacy among the dozens of emerging high-speed I/O protocols is requiring a lot of analog design artillery.

How much? Enough so that NurLogic Design Inc. of San Diego refocused the entire company over the course of the last year to focus on the analog elements of high-speed I/O, both standard-cell semiconductor intellectual property (IP) and a new unit focused on outsourcing the design work entirely.

"We've always had a heavy focus on delivering standard-cell libraries for I/O technology. And how we've stood out and been different is our mixed signal design expertise. We have the analog expertise in-house, and we approached any of our IP with mixed signal in mind," said Darla Berkel, product marketing manager for IP at NurLogic.

"Our analog segment has been the PLLs, the DLLs, our work in CDR, the clock data recovery area. But over the last year, we've really refocused the company to address specifically the high-speed analog element.

"We're taking it up a level, putting much more focus on high-speed I/Os, the high-speed bus and communications core interfaces," Berkel said. "We're developing the SerDes (serializer-deserializer) to operate within XAUI, within the InfiniBand standard and within HyperTransport."

Benny Malek, vice president of engineering at NurLogic, said clock data recovery (CDR) is a very complex and delicate analog task.

"At 3.125GHz (the Gigabit Ethernet, InfiniBand and Rapid IO realm), clock data recovery requires a very sophisticated PLL, and even the delay locked loop," Malek said. "This incrementally delays the clock in order to capture the data that's available to you. At these speeds, this data is only available for 300 picoseconds, and you need to capture that data within that window.

"These are very, very challenging issues," Malek said. "You need to sustain a data stream of 2 to the 32nd (power) cycles ... If you lose the synchronization, (the system doesn't work as intended). Clock data recovery is a very, very critical element of these interfaces.

At EDA giant Cadence Design Systems Inc. of San Jose, the design approaches for such work are being closely watched.

Henry Chang, architect of Cadence's SuperChip initiative, said that the design challenge comes in because fab process engineering has made the circuits so much faster.

"Back on the silicon, (the analog component) actually looks very similar (to what has come before). You have the same kinds of components, the differential signals, the PLLs. And the tool set is very similar. The process advancements are really what they are leveraging to be able to get these speeds.

"In the analog space, design in the analog world really hasn't changed much," Chang said. "One thing people are doing now is more behavioral modeling. It used to be analog design was focused more at the transistor level... Now they might start by writing a behavioral model either in Verilog-AMS or VHDL-AMS since those AMS languages can give them a link to verification at the protocol level."

So, once this precious analog IP has been created, companies are looking to make it more reusable.

Today, Newark, Calif.-based Prolific Inc., which makes software that lets companies create standard-cell libraries that they can plug into a synthesis/place&route IC design flow, will begin supporting mixed signal standard-cell technologies.

The wealth of activity in high-speed I/O was a major driver in Prolific's decision to support mixed signal standard-cell creation, said Dan Nenni, vice president of sales and marketing at privately held Prolific.

"(We) have seen mixed signal standard-cell libraries grow from 50 cells to more than 250 cells in a very short amount of time." Nenni said. One of the most popular mixed signal standard cells is for the guard rings, which isolate analog functions from the noisy, fast digital logic nearby; that's especially true in high-speed I/O. Such guard ring structures are also needed to build in resistance on the analog side to electrostatic discharge, commonly known as ESD.

Prolific's ProGenesis 2001 software allows for the creation of multiple power rails to isolate the noise between the digital and analog domains and the handling of complex design rules, such as arbitrary transistor shapes, additional design layers for analog integration and complex contact/via stacking rules. It also retargets the library according to changing design requirements and design rules in a matter of hours, Nenni said.

"Prolific's ability to make design and process optimizations to a complete mixed signal library within hours is key for evolving BiCMOS process technologies," said Andy Franklin, library manager at National Semiconductor Corp. "This makes it possible to create a solid design and easily maintain it as the layout design rules are refined during the development cycle."

Programmable logic suppliers, in their ongoing bid to win more networking and system communications customers, have been gearing up for the high-speed I/O wars, and finding out about the dedication analog expertise can take.