NeoMagic Licenses MIPS

Electronic News, August 28, 2000

NeoMagic Corp., Santa Clara, Calif., has announced that it has licensed the MIPS32 4K processor core family for use in Internet Appliance applications. The agreement includes a license, or an option to license, the entire family of MIPS32 4K 32-bit processor cores ranging from the low-power MIPS32 4Kp to the compact MIPS32 4Km and the high-performance MIPS32 4Kc. The first core to be used in the company's Internet Appliance applications will be the MIPS32 4Kc 32-bit processor core. Code-named Jade, the MIPS32 4Kc 32-bit processor core implements all of the features of the MIPS32 architecture, which incorporates all of the previous MIPS I and MIPS II ISAs. Jade also includes several new features from the R4000 and R5000 class of MIPS 64-bit processors such as conditional moves, prefetch, and privileged mode instructions. Key embedded-system applications functions such as MAC are directly supported with MADD and MSUB instructions. In addition, instructions such as "count-leading 1s and 0s" are included to enhance data manipulation algorithms and floating point software emulation operations. "Philips Semiconductors has considerable knowledge of the requirements for advanced system-on-a-chip needs as well as the full range of processor options for that market and has chosen the MIPS architecture," said John Bourgoin, chairman and chief executive officer at MIPS. "I am particularly pleased that Philips Semiconductors has chosen the MIPS64 20Kc core to serve their high-performance requirements."

Atmel Adds Teak DSP Core

Atmel Corp., San Jose, has licensed DSP Group's Teak DSP Core for use in the design of high-performance DSP systems-on-chips in the areas of speech and audio processing; multimedia; wireless, high-speed modems; and telecommunications applications. The Teak is a high-performance, 16-bit, fixed point DSP core using a Dual MAC architecture that enables peak performance of 260 MIPS. Featuring a parallel instruction capability, the core can handle double-word memory read-and-write instructions as well as perform high-speed interrupts and fast context switching. The Teak core also includes an extended program addressing space and new instructions that accelerate the performance of various DSP algorithms. The Teak DSP core provides several levels of modularity in RAM, ROM and I/O to allow for efficient DSP-based ASIC development. The core itself is designed in a single-edge clocking system, which allows the use of full or partial scan-testing methodologies. Emulation, debugging and testing are also supported via JTAG. When implemented with Atmel's 0.18-micron CMOS design rules, the Teak core occupies only 1.5 mm2 and consumes about 150 milliWatts.

Coreum Tech Licenses TriMedia TM32 Core

Coreum Technology Inc. has announced that it has licensed the TM32 VLIW processor core from TriMedia Technologies. The TriMedia 32-bit embedded processor cores, of which the TM32 is the latest implementation, are designed for integration into system-on-a-chip products and support a standard real-time operating system. The TriMedia VLIW architecture is applicable to media processing tasks such as encoding/decoding MPEG video streams, encoding/decoding multichannel audio streams, or demultiplexing/multiplexing broadcast transport streams.

The architecture processes up to five operations in every clock cycle without the costly control logic typical of superscalar processors, according to TriMedia. The instruction set architecture is optimized for media processing with special data-parallel operations as well as a full set of integer and floating point operations.

The TriMedia VLIW memory system features a 32Kbyte instruction cache and a 16Kbyte data cache. Instructions are stored in a compressed format in the external memory and cache, then decompressed on-the-fly during execution. The data cache is a pseudo dual-ported design, allowing execution of any pair of load/store operations in every cycle. This design is intended to optimize data availability to the CPU core.