Synapsys buys Co-Design for $36M: EDA startup valuations plunge, pressure mounts

Electronic News, Sept 2, 2002 by Gale Morrison

The Synopsys acquisition of Co-Design Automation last week sent shivers down the spines of EDA entrepreneurs across the design technology spectrum.

Co-Design is one of the best-connected and highest-profile next-generation design companies. It has supporters at Intel and throughout the standards group Accellera and easily five years of work in hand. But the selling price was a mere $36 million in cash, notes and assumed options.

Where does that leave the other 90 or so privately held EDA companies with ever-diminishing venture capital stockpiles and the daunting task of selling into the worst cap-ex environment electronics has ever seen? And what's to become of their IPO plans?

Despite the miserable economic environment, EDA startups have been holding out for much higher acquisition prices and sticking to their IPO plans in hopes that bigger companies and aggressive investors eventually will pay more. But analysts and big EDA companies say those startups--even those with some admittedly hot technology--are living in the past.

Just like lots of other companies in the dot-com boom era, EDA startups compared themselves against irrationally exuberant valuations. In 1996, Epic Design Technology was sold to Synopsys for more than $350 million. In 1998, Ambit Design was sold to Cadence for more than $300 million. Last year, Verisity Inc. was the single best-performing IPO.

To be fair, executives have been adjusting their expectations this summer. Five-times yearly revenues by last week were down to three-to-five-times yearly revenues as the metric by which all acquisition offers are judged. Still, in this environment, assured statements that one's company is on an IPO track are beginning to look preposterous.

"I'm very careful not to go around saying that we're going public because at this point you just look stupid," said one marketing VP in the synthesis space.

Aside from this financial soul-searching, the Co-Design buyout prompted a fair amount of verification and system-level design technology soul-searching, too. For several years now, EDA has been wrangling with how design would move up an abstraction level from the Verilog and VHDL HDLs.

With the ceaseless march of Moore's Law, a leap above register transfer level (RTL) was seen as a must. At the same time, the verification task has become so complex that the use of specific languages as well as C/C have become a standard practice. Verisity made its way to that Wall Street IPO performance on the merits of its "e" verification language.

Meanwhile, Co-Design always insisted that any variant of C--CoWare C, SpecC, CynLib--didn't stand a chance for the verification task. One-time SLD competitors CoWare and Forte Design Systems both said last week that the Synopsys acquisition proves Superlog, which is the basis for the emerging System Verilog standard, is complementary to a very much alive and well SystemC. Still, each tried to pigeonhole Co-Design and System Verilog as a verification-only story.

"SystemC is used for system-level design, embedded software development, modeling and high-level verification. System Verilog is used heavily for test-bench automation," said Alan Naumann, CEO of CoWare. "Any large EDA company interested in hardware verification of ASICs could benefit from this technology.

"The pertinent question is how will the verification language wars take shape, including Superlog, Vera and Verisity's E language," he said.