Beyond Physical Synthesis

Electronic News, Sept 11, 2000 by Gale Morrison

Sequence ships its Copernicus advanced timing optimizer

After 18 months in development yielding two patents (with eight more pending) and with the high-profile backing of LSI Logic Corp., Sequence Design Inc. today formally starts shipping Copernicus, its interconnect-driven timing optimizer for the most advanced IC design flows.

The release of the $200,000-per-seat Copernicus is noteworthy for two reasons. First, this product bucks the industry trend that assumes that physical synthesis will yield sub-0.25-micron timingclosure. Second, Sequence's business plan may be one of the first in which an EDA firm has said explicitly that the expertise to do this optimization is itself a marketable commodity. Sequence is saying that its software intellectual property (IP) will contribute revenue in the near term.

For the last 18 months, Ambit Design, Magma Design Automation, Cadence Design Systems, Monterey Design Systems and Synopsys Inc. have been proselytizing for a new ICdesign paradigm. Their credo says that with line-widths any smaller than 0.25 micron, physical information like gate and wire capacitance must be used in accomplishing the design basics of synthesis, place-and-route (SP&R). Only then, this thinking goes, will a chip design be able to reach its presynthesis timing goal. Ambit Design was sold to Cadence for $240 million in stock and Magma and Monterey combined have raised about $80 million in venture capital with their technology proposals around this idea.

But Sequence didn't buy it. Copernicus is the platform that more than half of Sequence's employees have devoted themselves to over the same 18 months. The idea behind it is that the physical information you can provide for even physical synthesis, much less the wireload models of traditional flows, is only one-dimensional capacitance. Three-dimensional capacitance isn't known until after final routing, especially when you are dealing with line-widths of 0.18 micron and below.

The Sequence software takes in routed designs--in whichever format their SP&R method produced: .lef, .sdc, .lib or .def-- and pinpoints within those designs where wire drives could be created to improve performance, said Eric Filseth, vice president of product marketing at Sequence. Copernicus outputs very specific, detailed directives to whichever place-and-route (P&R) tool was used, and the design is tightened up, Filseth said. Sequence says performance improves 15 to 20 percent in designs done with the latest physical synthesis flows and more than that with the conventional Synopsys DC-to-Avant! or Cadence P&R flow.

Leading-edge customers will quickly pay up the $187,500 that each Copernicus license costs, on top of what they are being asked to pay for the new physical synthesis seats, which averages about $350,000, according to Alain Labat, Sequence's chief executive officer. Labat also sees greater opportunity for licensing revenues around the company's Copernicus patents. (Ultima Interconnect Technology is already a licensee, in exchange for Sequence dropping the lawsuit it filed this spring.)

"It's very much in our strategy ... part of the business model for Sequence sees revenue from the licensing of our patents," said Labat last week from Tokyo, where he was officially opening the company's Japan office.

Filseth explained what's so special about this EDA technology.

"Our IP is really around the algorithms that make those specific changes to placement and routing while keeping the space for those wires neutral," Filseth said. "Now, could you integrate this? Probably. But it's not a trivial problem to go back ... and optimize the gates and buffers so that you get this kind of improvement while touching only, say, 5 percent of your design."

Labat said Sequence's business plan also calls for one of the newer software revenue models EDA is seeing more often. Sequence will seed certain ASIC design centers--NEC Corp.'s and LSI Logic's, among others--to expand the use of Copernicus and then will earn its money through a per-design fee.

Gary Smith, principal EDA analyst at GartnerGroup Inc.'s Dataquest unit, isn't quite as optimistic for Copernicus though. "I see this as an interim product," said Smith. While the physical synthesis players battle it out and put this same technology into their offerings, Copernicus has a chance, but not an open field, he said.

"Sequence's market window is about 18 months long. After that they will be able to sell the technology to one of the winners--maybe one of the losers--but I don't see the possibility of a general licensing scheme. All five of the IC implementation vendors are working on the technology. Copernicus could be the best now, but for how long? That's the question.

"These optimizers will be completely integrated into the IC implementation tool set within 18 months," Smith concluded.