ACM Moves Into Wireless Designs

Electronic News, Sept 18, 2000 by Paul Master

Embedded applications turn to ACM rather than conventional or reconfigurable ICs

The adaptive computing machine (ACM) is among the newest IC technologies targeted at the embedded wireless and mobile communications markets. An ACM chip adapts continuously so that within a fleeting moment, ACM changes its architecture hundreds of times, emulating a much larger device over time.

An ACM fabric allows software algorithms to build and then embed themselves into the most efficient hardware possible for their application. Because this eliminates much of the code overhead such as memory fetches and ALU/MAC set-up procedures, these algorithms run in hardware at hardware speeds rather than as software running on top of hardware. This constant conversion of algorithms into hardware means faster and more efficient operation as compared to conventional chip technology.

ACM at Work

ACM technology gives developers paradox-busting capabilities with high-performance, low-power consumption, small size, low cost, and an extremely high level of adaptability as compared to rigid, conventional IC technologies. ACM's adaptive nature allows a single handset to perform a wide variety of tasks with media-rich applications including voice, data, image, and video. Silicon becomes a function of its input, rapidly adapting on-the-fly, at blazingly fast speeds, to create a specific hardware engine for each task. In contrast, conventional IC technologies such as ASICs, FPGAs, and [micro]Ps/DSPs offer fixed architectures capable of performing only those functions originally designed into the product. ACM's adaptability also enables multimode handset operation that is impervious to constantly changing standards or ever-improving software algorithms.

Compared to Reconfigurable Computing

There are misconceptions within many design circles about FPGA-based reconfigurable computing (RC) and adaptive computing, and their respective targeted applications. ACM adaptability far exceeds that of FPGA and reconfigurable-datapath computing methods. ACM has greater than l00,000-times-a-second adaptability at extremely low-power consumption levels as compared to FPGAs. Also, ACM technology delivers ASIC-like performance and power consumption with software-like device programming.

There are two RC approaches: conventional first-generation FPGAs and second-generation FPGAs. The most recently announced high-density FPGA is primarily aimed at replacing gate arrays and ASICs. The engineer spins an FPGA design a couple dozen times during development and then puts the bit file into flash memory. That file remains static until a new download is needed, for instance, to fix bugs.

Historically, FPGAs used for this purpose are designed to be whole-chip reconfigured. In this case, the chip is stopped, another complete bit file is serially downloaded, and the chip is restarted. Since this is very time and power consuming, newer FPGAs are designed to be partially reconfigurable along independent chip columns or rows. However, most designs are comprised of many smaller internal pieces and each piece is comprised of a geometric pattern that is far from having a column orientation.

Therefore, when such pieces are to be reconfigured, the necessary bit file spreads across many columns, where other pieces of the chip design, not needing to be changed, are situated. So, unchanged parts of the design are reloaded anyway. Also, any internal design piece that communicates information through a column that's being reconfigured must be interrupted and restarted once the column-based bit file is restarted. The result is virtually a total recreation of the earlier FPGA whole-chip reconfiguration process.

Second-generation FPGA-based RC technology is divided into two categories. In the first case, the RC device includes an on-chip embedded processor to augment the conventional FPGA fabric in a system-on-a-chip (SOC) product. In effect, this is the next logical evolution of moving from a board design to an SOC, so not much actually changes the power consumption and reconfiguration times associated with FPGA-based reconfigurability.

In the second case with reconfigurable-datapath devices, the interconnect can be reconfigured at a reasonably high data rate. Design issues arise because a reconfigurable-datapath device is a vector processor, ideally suited for data flow with small amounts of control content. This makes it well suited for base station designs since some of the processing can be vectorized. However, only a small amount of overall C code can be vectorized and that places design limitations on the use of RC technology in a large number of applications.

Compared to Conventional Technology

Adaptive computing compares even more favorably with conventional microprocessor, DSP, and ASIC technologies. Computational power efficiency (CPE) is a metric used to illustrate the advantages and disadvantages of today's design techniques. CPE is the ratio of the number of gates actively working to solve the given problem to the total number of gates in the device.