Convergence Apps Need Embedded VLIW IP Architecture

Electronic News, Sept 18, 2000 by Jim Thomas

Today's consumer electronics systems can best be characterized as a rapid convergence of networking, high data rates and complex and rapidly evolving system functions--including digital audio and video into functional units such as set-top boxes (STBs), digital TVs, or home portals.

These systems now require a high degree of flexibility and time-to-market that can only be achieved with software programming. However, the required level of performance is not attainable with traditional microprocessors. Very long instruction word (VLIW) processing, which can execute many instructions in parallel all in the same clock period, is the best solution for this convergence because VLIW possesses potentially enormous compute power with very small chip area and low power that is required for flexible, cost-effective consumer solutions.

Design flexibility and a good price/performance ratio are paramount in these feature-rich convergence systems. Flexibility is important because these systems need to be, for example, a browser one minute, a Web phone the next, and a video-conferencing application the very next minute. Designers have performed these applications in dedicated hardware, but it is not a flexible approach.

VLIW is the most silicon-efficient architecture known for high performance. Although VLIW machine architectures have been known since the early 1980s, the initial application in general computation areas was difficult and initial research and development showed limited improvements. The problem has been traced back to the relatively low inherent parallelism, largely due to the fact standard C code was used for general-purpose computation. Therefore, an accepted belief was that an instruction-level parallelism of greater than two was hard to achieve. Since then, the general-purpose computing world has accepted scalar RISC architectures and superscalar architectures with limited instruction-level parallelism.

The inherent benefit of VLIW architectures is the potentially enormous compute power at very small chip area and low power compared to superscalar architectures. The general field of DSP and multimedia processing has always been an area with enormous computational requirements, while the power consumption should stay limited. Several VLIW architectures for the multimedia domain have emerged that are very effective. These architectures that allow instruction-level parallelism ranging from four to eight are becoming more popular.

It is critically important for the processor to achieve a natural and efficient integration of single-instruction multiple data in the programming environment with languages like C and C . This allows the complete application to be written without resorting to a nonportable, tedious, and error-prone process of programming in assembly language, which is now the programming environment for some VLIW processors.

Design Issues

System engineers opting for conventional processors are confronting performance limitations and unacceptable design tradeoffs. Complex control hardware required in superscalar processors to detect and schedule operations makes them expensive. Plus, poor scalability to higher parallelism and high silicon costs limit the use of these superscalar architectures for future computationally demanding applications.

Even the most powerful RISC microprocessors, highly optimized and running at very high clock rates, do not possess the necessary processing power for handling difficult multimedia design requirements in next-generation systems. A way to increase performance in these RISC-based video designs is to add a full DSP or sophisticated video accelerator. With this approach, the trade-offs the system designer faces are a highly complex and costly design, plus inflexibility for altering the design when standards change.

Evaluating IP and ASIC Designs

Therefore, it is critical for engineering managers to carefully evaluate their system requirements and select the right design approach to minimize risk of failure and to preserve their engineering investment. For consumer systems, foremost considerations are cost, time-to-market, flexibility to support rapid product evolution and significant minimization of product risk. A design team may feel the right processor intellectual property is not available, and so it launches into a six- to 12-month ASIC design. Pitfalls in this case are a fundamental lack of flexibility when an error occurs or when upgrades to a next generation are required. On top of this, engineering management loses its initial investment due to ASIC respins.

Conversely, with a proven available intellectual property core that's well supported, system designers can realize a considerably improved time-to-market with far less risk. For example, if there are minor errors in a complex intellectual property-based SOC design, system engineers usually can fix them with software workarounds. Moreover, the initial investment is not lost because cores, market-specific intellectual property and associated software can be continuously reused and upgraded. Intellectual property vendors like TriMedia Technologies have roadmaps for higher-performance cores to assist system OEMs to ensure their intellectual property investment well into the future.