The middle ASICs: the gap between FPGAs and ASICs is no longer the forgotten world - Semiconductors - field programmable gate arrays, application-specific integrated circuits

Electronic News, Sept 23, 2002 by Richard Wilson

Configurable and custom chip suppliers are getting interested in a new type of customer. They aren't designers of volume ASICs, which are churned out by the millions and require a huge design effort and investment. Nor are they designers looking for a smaller number of very high-performance FPGAs and with the budget to pay for them.

It is that middle ground of the ASIC market where performance and cost are traded off against each other. It is that part of the custom market where everyone's on a budget--be it megahertz of performance, megabit of memory or thousands of dollars. FPGA suppliers were the first to move in. Market leaders Xilinx and Altera have both introduced programmable products intended to reduce development costs for users in the last 12 months.

Then it was the turn of the gate array companies, which reasserted their claim over the space between FPGAs and standard ASICs with talk of new product offerings and new process technologies.

It wouldn't be long before a volume ASIC supplier made its pitch for this middle market, and it came with details of LSI Logic's RapidChip custom platform, which combines standard ASIC cells and IP cores with user-configurable logic and on-chip memory.

The reason for all this interest in what was just a few years ago the forgotten market between FPGAs and full-blown ASICs is the new cost-consciousness imperatives of custom silicon designers. While applications in high-speed networking, digital set-top boxes and 3G basestations require custom chips of significantly higher levels of performance, there are no longer the unlimited development budgets available to complete the design at any cost.

From the ASIC end of the market the problem really struck with the move to sub-0.25-micron process technologies. "There was a dramatic increase in ASIC design cost with the move from 0.25- to 0.18- and 0.13-micron technologies," said Ronnie Vasishta, VP of technical marketing at LSI Logic. "The typical cost of a mask set for a 0.13-micron ASIC is around $700,000.

"Complexity of design is becoming a barrier to some people in the ASIC market," he added.

LSI Logic's approach with its RapidChip platform is to combine a standard-cell ASIC design with uncommitted logic arrays and memory in a custom-chip platform that the company is aiming specifically at communications and digital consumer applications.

Vasishta said at six months the design start to product cycle is comparable to an FPGA and about half the time of a standard-cell ASIC. Also development costs can be 20 percent of a normal standard-cell ASIC.

Fully compatible with the company's existing ASIC platform, the full range of software IP in its CoreWare library is also available to be used on the platform.

Renewed interest in the middle market has prompted some gate array suppliers to step up investment in the lower-cost ASIC technology. Prototyping ASIC supplier Chip Express is reinventing itself as a more broad-based supplier of gate arrays. Supporting the change in tack has been an investment in 0.18-micron process technology that will come onstream by the end of the year.

Richard Wilson is an editor with Electronics Weekly, a sister publication to Electronic News.