Design for System-on-a-Programmable-Chip

Electronic News, Jan 15, 2001 by David Greenfield

System-level design for complex PLD technologies

Advances in PLD size, speed, and the accessibility of easy-to-use embedded processor cores and other intellectual property (IP) by themselves are not sufficient to enable system-on-a-programmable-chip (SOPC) design.

It takes a clearly designed system-level methodology dealing with system-level complexity to deliver the time-to-market benefits that PLD technology enables.

In the past, a completely integrated design entity included design entry, synthesis, simulation, place-and-route (P&R), and timing analysis. Today, these same customers require use of best-in-class synthesis tools, best-in-class simulation tools and best-in-class timing analysis tools. PLD P&R tools must meet this changing requirement in a way that makes the entire design methodology look much more ASIC-centric in orientation. If this new PLD methodology is correctly designed, it will enable adoption of IP more quickly than ASIC technology could provide and support the flexibility and customization that only programmable technology can deliver.

Use of IP is now prevalent in high-density devices. While customers have used bus-interface functions (such as 66MHz PCI) and DSP functions (like finite impusle response (FIR) filters) for several years, three fundamental changes have recently emerged. First, application-specific compilers now deliver tremendous functionality and flexibility for IP. A new FIR filter compiler, for example, enables design of a filter with any number of taps and includes a built-in coefficient generator supporting coefficient widths from 4 bits to 32 bits of precision. The FIR compiler also supports decimation and interpolation options and serial and parallel arithmetic options. The result is a filter optimized for the exact performance and area requirements of a user, which can also be easily modified and re-evaluated to accommodate changing system requirements.

The second important shift in enhancing the design methodology involves the interfaces now provided to industry standard tools. This FIR compiler, for example, now also generates MATLAB, Simulink, VHDL, and Verilog HDL simulation models, enabling tighter links with powerful tools. Similar application compilers are emerging to support DSP applications like Reed-Solomon error-correction.

The third significant shift involving IP is the emergence of embedded processors optimized for PLDs. It's only with high-performance processors that the true potential of SOPC design capability is really possible. In a perfect world, a designer would simply generate C code to embody the system specification and the tools would be smart enough to partition some algorithms in the embedded processor and synthesize logic for the remaining algorithms. Unfortunately, the tools are not yet this sophisticated. Integrating embedded processors within PLDs exposes the designer to a plethora of new complexities. The new design methodology must address issues like modeling, integrating processor and PLD design entry, and intelligently developing bus-interface elements to optimize system performance.

To optimally solve system-level problems, the tools must provide accurate and complete models of how a processor core interacts with memory, peripheral devices, and I/O blocks. Designing with a hardcore processor often requires a bus-functional model of the processor describing the particular system bus operations, timing, and interface to the other blocks within the design. Soft-core processors require the right behavioral models to verify that the processor subsystem timing specifications are met in the actual PLD implementation. Access to VHDL or Verilog simulations of the entire SOPC design, behavioral simulation, and support of VHDL and Verilog test benches is also necessary.

A key to ensuring successful use of embedded processors in PLDs is developing an intuitive methodology for choosing a specific processor, selecting all the applicable peripheral functions and external memory controllers, and defining the memory map.

Once the peripherals and memory map are selected, issues such as generating C-code for the processor, RTOS selection and peripheral drivers become critical. When the PLD gets programmed, it must be programmed with a device file that integrates the embedded processor initialization code with the traditional PLD initialization file. Success requires a methodology that integrates these elements into a coherent process.

It's not just the IP elements of the design methodology that are changing. In many other ways the design methodology is closely aligning to the existing ASIC methodology. Customers are asking for tools that were previously only relevant for ASIC design. Just last year, functional and timing simulation was adequate for most PLD customers. Customers are now looking to use behavioral simulation tools to optimize the design process and to meet this need. These tools also provide test-bench capability to accelerate the simulation process. Designers are looking to balance the need to increase simulation speed without compromising accuracy and effectively compress the amount of logic up and down according to the amount of "resolution" required. Simulation tools like ModelSim enable the designer to intelligently control this balance.