Adaptable Computing Conquers Tech Barriers

Electronic News, Oct 9, 2000 by Steve Cox

For the first time since the advent of the microprocessor in 1971 and Moore's law in the early 1960s, the industry is facing serious technology barriers. The intense drive for greater performance and lower power consumption, and the limitations posed by today's MPU and DSP architectures are building these barriers, and thus casting serious doubts on conventional MPU/DSP/ASIC design methodology. To date, the industry has marched in lockstep to "a shrink and integrate" approach based on Moore's Law.

The industry is rapidly coming to a point where it cannot physically continue to shrink, integrate, and produce the advanced types of chips emerging applications demand. Newer and more sophisticated MPUs and DSPs cannot continue to run at those blazingly fast speeds at the expense of higher and higher power consumption.

Moreover, as semiconductor companies continue to shrink and integrate, the chips get increasingly larger, and as new functionality is added, they take longer to design, manufacture, and test. In fact, testing has become more of a job than the actual design itself. Part of the reason is that the simulation of these designs is performed on workstations with the simulation operations running at a very slow 1Hz. These emerging issues are especially problematic for future generations of mobile consumer and wireless communications applications.

Take for example a GSM/TDMA/CDMA cell phone design. All that baseband functionality should go on one chip. But it is difficult, if not impractical, to design in all this functionality with current MPU/DSP/ASIC technologies. The problem is CDMA, TDMA, and GSM are all different digital protocols that require different baseband processing. CDMA operates differently than TDMA, which works differently than GSM. In this case, the system engineer has to develop an architecture and implementation to support all these protocols and then create the test procedures. Attempting this design feat utilizing conventional MPU/DSP/ASIC design techniques incurs inordinate design engineering and testing time.

The second problem with taking the conventional MPU/DSP/ASIC design route is once the system is designed, it is all but cast in stone and is not easily changed. This, in itself, poses a further problem, because the design cannot be changed as it moves further in the design cycle. In this instance, the design has to be perfect up front, which calls for a large amount of up-front testing as well. Consequently, this methodology keeps an OEM from quickly turning a product and many OEMs are intent on quickly turning over their product lines. Conventional design approaches work against being able to spin a product every six to 12 months.

A third, and one of the biggest problems with fixed ASIC designs, is the inability to fix bugs remotely in the field as they relate to circuitry inside the ASIC, which can cause a costly product recall. And finally, today product updates and upgrades in the field are difficult at best.

Ideally, to resolve these design issues, the system engineer wants silicon that can be adaptable on the fly via constant algorithmic downloads.

For example, in an adaptable computing machine (ACM), the same chip's "effective" architecture can be constantly changed to be virtually any function or group of functions, depending on the algorithm or set of algorithms downloaded at any given point in time. This approach allows the system designer to test the functionality in real-time, rather than having to incur considerable front-end simulation time.

ACM technology also allows the system engineer to push design decisions further downstream in the design cycle, for example, decisions relating to an audio or MPEG codec. If the design is implemented in an ASIC, then there is no opportunity for change. But with a microcoded ASIC or DSP, the designer has a better chance. Unlike a fixed ASIC, MPU, or DSP architecture, an ACM-based design gives the designer wide latitude since functionality isn't cast firmly in silicon. Conversely, since the silicon is adaptable via algorithmic downloads, the silicon can feature a virtually endless list of different functions (see figure 1, page 38).

Moreover, in most RISC MPU and DSP cases, the system engineer must "bend" a given algorithm to fit a particular architecture. In effect, the design engineer or developer must take a given algorithm and try to fine-tune the code so that it runs as efficiently as possible on a particular MPU or DSP architecture. An ACM architecture, on the other hand, permits the system engineer to run a given algorithm in its most efficient form. In other words, the processing work required to efficiently run the code is performed in a few clock cycles, rather than in an inordinate amount of clock cycles.

But running an algorithm on a conventional DSP or MPU incurs a considerable number of clock cycles, primarily due to instruction fetches and operand read/writes. In fact, most of the cycles done by MPU and DSP implementations are "overhead" just to setup the actual work output desired.