VLIW Processors Tap into Internet Audio/Visual

Electronic News, Nov 13, 2000 by Mohammad Ayub-Khan

The standard is independent of network topology and H.323 terminals can communicate over LANs via hubs or LAN switches, over such local or remote Internets as routers and bridges, and over dial-up connections. Voice-over-Internet Protocol is one particular H.323-based application that is quickly gaining industry popularity. H.323 provides various service levels of multimedia communication over a data network. Examples include voice only, voice and video, voice and data, or voice, video, and data communications. All of these provide collaborative tools in support of the virtual corporation paradigm, via intranets, extranets or the Internet. For example, with H.323-ready devices, on-demand interactive multipoint multimedia conferences can be established without the need for reservations.

As shown in the chart, the VLIW processor connects to the Internet via Internet/Ethernet adapter on a daughter card interfaced to the processor's synchronous serial interface (SSI). The SSI unit interfaces to an off-chip modem analog front-end subsystem, network terminator, analog-to-digital converter, digital-to-analog converter or codec through a flexible bit-serial connection. The hardware performs full-duplex serialization/deserialization of a bit stream from any of these devices.

Any front-end device connected here supports the transmission and reception of data and initialization via the SSI. This SSI unit supports a wide range of modem, network and/or FAX protocols. This is possible because the VLIW media processor implements the communication algorithm in software and the analog interface is off-chip. The SSI unit permits the system designer to implement virtually any communications standard. In this instance for an Internet connection, the system designer uses an Internet/Ethernet LAN connection by implementing an H.323-based daughter card with supporting hardware.

The heart of this Internet connection design is the 32-bit DSP/CPU core of the VLIW media processor. This DSP/CPU implements a 32-bit linear address space and 128 fully general-purpose 32-bit registers, which aren't separated into banks so that any operation can use any register for any operand. The VLIW instruction length allows five simultaneous operations to be issued every clock cycle. These operations can target any five of the 27 functional units in the DSP/CPU, including integer and floating-point arithmetic units and data-parallel multimedia operation units.

The VLIW media processor's operation set includes all traditional microprocessor operations. Multimedia operations are also included that accelerate standard video and audio compression and decompression algorithms. As just one of the five operations issued in a single processor instruction, a single "custom" or "media" operation can implement up to 11 traditional microprocessor operations. These multimedia operations combined with the VLIW architecture provide the designer with a very high level of throughput for multimedia applications.