The future of the data plane in networking equipment

Electronic News, Nov 19, 2001 by Tom Riordan

CURRENTLY, THE COMMON goal among processor developers targeting the communications market is to perform packet processing at OC-48 line rates where, in addition to the raw speed requirements of OC-48, service providers demand content-aware capabilities such as intrusion detection, load balancing and quality of service.

With OC-192 technology quickly becoming a reality, network equipment designers are already thinking beyond OC-48 and are searching for processing solutions that provide a clear and viable scalability path for the data plane. Some companies have professed that an all-in-one programmable solution meets these demands, while others have their hopes riding on the hardwired, ASIC route.

In reality, to reach these unprecedented line rates and time-to-market requirements, network equipment designers must adopt a hybrid approach. This hybrid approach relies on the quicker and more maintainable programmability of a fast general-purpose CPU and the wire-speed capability of a data-path application-specific standard products (ASSPs), creating a division of labor in the data plane.

A little more than a year ago, network processor vendors jumped on the scene declaring OC-48 capabilities and how their devices could handle all packet-processing functions in software, excelling where the traditional microprocessors fell short. What a difference a year makes. Now professing support for OC-12, the network processor realizes it needs help and off-loads processing applications, such as packet-classification and forwarding, to a coprocessor to achieve OC-48 line rates.

Programming these network processors is also inherently complex because all of the architectures require low-level assembly language-controlled multiprocessing and multithreading to achieve decent performance. Portability is not even conceivable, really. Even the designer's solution discovery task becomes more difficult because of the variety of architectures to choose from--each with its own unique development environment. Programming time equals more money spent and missed time-to-market goals.

ASICs execute specific processing functions extremely fast, but because it takes roughly three years from design inception to market introduction, an ASIC is not always available that can deliver the packet-processing functionality needed by designers. The current generation, general-purpose microprocessors, such as those using the MIPS architecture, have the characteristics of flexible, portable and maintainable software that are synonymous with an industry standard and come with a plethora of third-party tools and applications. However, these traditional processors have lacked the performance required for the higher line rates.

The good news for network designers is that we now find ourselves at a point where content-aware devices have emerged as ASSPs and microprocessors delivering multiple gigahertz of performance, low-latency integrated memory controllers and high-speed packetized I/O ports have been introduced.

The graphics industry provides an interesting parallel in this evolution. As more graphic features were expected and the display resolution increased geometrically--much like line rates--the ASICs could not be modified fast enough. Programmable graphics solutions were then introduced to provide higher performance and meet the latest standards. These solutions failed in the end because a fast CPU with a highspeed ASIC was cheaper, faster and much easier to program. All it took was the standardization of features for the next-generation ASICs and software to displace programmable graphics engines.

Programmable engines found in today's networking equipment data paths will also be replaced by a much cheaper, faster ASIC coupled with a CPU closely linked off the data path. The ASIC handles the repetitive processing functions at wire speed and the CPU provides the flexibility for handling the exception and general processing tasks such as first-route failure and statistics gathering, respectively. This future data plane model offers designers an industry-tested road map to take networking equipment to OC192 and beyond.

Tom Riordan is the VP and GM for the MIPS Processor division of PMC-Sierra Inc. of Burnaby, British Columbia.