Tera systems signs top ASIC houses

Electronic News, Nov 26, 2001

JUST WHEN YOU THOUGHT THE "DESIGN PLANNING" SEGMENT of chip design couldn't get any more attention since the shoe dropped and Cadence Design Systems bought Silicon Perspective, Tera Systems rockets to the forefront today with a hat trick of endorsements from the world's three leading ASIC companies: LSI Logic, NEC Electronics and IBM Microelectronics.

Tera says that all three companies are now using Tera Form 2 to one extent or another. This turns up the heat on Cadence to get the SPC technology into Integration Ensemble; for Synopsys Inc. to get its product, code named Hidden Dragon, out of beta test; and for Magma Design Automation to work some magic on the BlastPlan product it announced last June at DAC.

It's all about the hierarchy. Not the hierarchy of EDA companies, that is, but approaching large chip designs by partitioning them and assigning blocks and problems into a hierarchy. These design planning solutions are but a slice of a wider hierarchical design transition that is cutting the wheat from the chafe in EDA, said Erach Desai of Desai Technology Research in Boston.

"If you don't address the hierarchy, you are not going to address the SOC problem," Desai said. He noted that Simplex Solutions, Nassda and verification house Verplex have all revamped their tools to convert the specific design tasks they address to a hierarchical problem. "It's got to be done," he said.