Sequence, Japan Researchers Modeling Interconnects

Electronic News, Dec 4, 2000 by Gale Morrison

SANTA CLARA, CALIF.-BASED Sequence Design Inc. reported last week that it and the Semiconductor Technology Academic Research Center (STARC) of Japan are collaborating to produce interconnect models for a standardized 0.13-micron silicon process.

STARC is an organization funded by Japanese semiconductor makers and includes Fujitsu, Hitachi, Matsushita, Mitsubishi, NEC, OKI, Rohm, Sanyo, Sharp, Sony and Toshiba.

The goal of the Sequence-STARC project is to create a common 130-nanometer design-rule specification for use by third-party library and intellectual property (IP) vendors in the creation of a single set of libraries or IP blocks that customers may use no matter which member fab line is targeted. This common design rule specification will also enable the major Japanese foundries to build standardized IP to share amongst one another. Sequence's Columbus software technology will be used in the work.

"Achieving the most accurate interconnect models is essential to being able to predict parasitic effects on timing of real silicon," said Koichi Fujita, general manager of Advanced CMOS Technology at Fujitsu Ltd., a member of STARC.