System Design Begins with C++

Electronic News, Jan 22, 2001 by David Park

San Jose

HARDWARE DESIGN IS now a bout to go through a significant design shift not unlike the change a decade ago from gate level to register transfer level (RTL) HDL design. Companies are realizing that the hardware and software domains must be designed with both domains in mind, not as separate pieces that can meet after both are completed. Since C++ is already the dominant language used by system architects and software engineers, it makes sense that the language of choice for hardware engineers should also be C++.

C++ adds significant value to the hardware design process. As designs have gotten progressively larger and more complex, RTL HDLs have been pushed to the limit of simulation performance and design abstraction. C++ is well suited to address those concerns. Not only can C++ support basic hardware design requirements such as component instantiation, multiple clocks, hierarchy and concurrency, but C++ also has the flexibility to create models at much higher levels of abstraction than HDLs for more efficient system-level modeling.

Simulation performance and design capacity are also significantly higher with C++ than with traditional HDLs. We have customers today that are using C++ to design ASICs and systems-on-chips (SOCs) as large as 3.5 million gates with simulation speeds up to 1,500 times faster than native-compiled HDL simulators. These performance gains are not just with high-level system models, but also with functional models that are directly implementable into VHDL or Verilog, ready for logic synthesis.

Until recently, the primary benefactors of this technology have been the companies in the networking and telecommunications markets. Companies such as Motorola, Siemens, and Compaq have turned to C++ tools and methodologies to help deal with the incredibly long simulation runtimes required of their nextgenera lion designs. By enabling them to create multimillion-gate, hardware-accurate, implementable models that simulate at speeds two to three orders of magnitude faster than native-compiled HDL, these customers use C++ to give themselves a strategic and tactical advantage over their competition.

The best part is that the C++ hardware design flow is very complementary to existing HDL design flows. In addition, designers still have all of the control of VHDL and Verilog, but now with the data abstraction of C++. Very complex data structures can easily be described using C++ that would be difficult, if not impossible, to describe with either VHDL or Verilog. Simulation using C++ is fast and free and it can be run on virtually any machine that has a C++ compiler. Support for standard waveform generation is also available, giving designers the ability to debug their designs with waveform viewers they are accustomed to using. Once the desired functionality is verified, C++ synthesis tools such as System Compiler quickly and efficiently synthesize the C++ design descriptions into either VHDL or Verilog and are ready for logic synthesis.

It is critical that EDA companies come together to develop a standard for C++-based design. Standards are necessary so that C++ simulations will match from vendor to vendor and so that intellectual property written in C++ can be shared across design teams and companies. These standards will make it easier for all EDA vendors to develop complementary tools that complete the design flow and will help HDL designers transition up to C++.

One aspect that we must not lose sight of in the course of our standardization efforts for C++ is that system architects and software designers use native C++. They do not use a hardware-based C++ class library as part of their design efforts. An industry C++ standard set of hardware design class libraries is only one facet of the system design problem. We must realize that whatever we do in the hardware design space with C++ is still just a subset of what the system design and software design community currently uses. Any standardization effort must include support for the full C++ language if we truly want to be able to address the larger issues of hardware/software codesign and system design and not just hardware design.

David Park is vice president of marketing at C Level Design Inc. in San Jose.