Wafer Scale Emerging

Electronic News, Jan 22, 2001 by Brandon Prior

Numerous configurations have been developed

Wafer CSPs or wafer-scale/chip-scale packages (WS-CSP) have been in development for more than five years. In 2000, approximately 260 million wafer CSP die will be shipped with an expected annual growth rate of 68 percent per year for the next five years. More than 25 distinct wafer CSP product configurations have been developed: some are tailored to the needs of specific die functions, others are aimed at ease of manufacture and lowest cost.

In 2000, the electronics industry consumed 1.8 billion die in flip-chip form and 14 percent of these were wafer CSPs. The principal difference between a wafer CSP and a flip-chip die (according to Prismark's definition) is that a wafer CSP is post processed after the fab with larger bump pitches, whereas a flip-chip die will be completed in the fab. Flip-chip designed die will only need to have underbump metallurgy (UBM) and bumps placed on it before assembly. The reason for using wafer CSP technology is that peripherally designed die can be transformed into a standard bump or ball footprint that is compatible with current PCB layout rules, device test practice, and assembly practice. On the other hand, a flip-chip device tends to have a bump layout that is designed to maximize utilization of silicon and electrical integrity, with assembly and test being secondary issues.

In practice today, wafer CSPs tend to have ball pitches of 0.5mm, about the minimum that the printed circuit industry and current test/assembly practice can support. Flip-chip die typically have pitches of about half this value at 0.25mm.

This current wafer CSP pitch limitation of 0.5mm means that wafer CSPs tend to be limited to low leadcount devices (less than 30I/O) or larger area die with medium leadcounts (memory). Flip-chip devices can have leadcounts of several thousand I/O. In the long run the distinction between flip-chip and wafer CSP will no longer be discernable as pitches well below 0.5mm will be able to be supported by the board fabricators, the test community, and the assembly community.

Integrated Passives

One very important application for wafer CSPs is integrated passives. Prismark predicts that this will in fact be the major wafer CSP application in terms of die count. "Die" is a somewhat euphemistic description since the "die" in question may be a combination of diodes and capacitors on silicon, thin-film on glass, or thin-film on silicon. However, each is recognizable as a flip-chip-type device even if the "wafer" is a 200mm x 300mm sheet of glass.

The principal advantages of wafer CSP technology for passives are low cost and small physical footprint. There are many companies that are active in this area: Intarsia, Bourns, Murata, STMicro, International Rectifier, and California Micro Devices. Flip Chip Technologies (FCT) actively supports several of these companies with bumping services.

Memory

A great deal of energy has been devoted to wafer CSP approaches for memory. For fast memory, wafer CSP is potentially an ideal application. Electrical performance (mutual inductance and capacitance) has become critical with double data rate (DDR) architectures favoring direct access to the center of the die via bumps. The die are large enough to accommodate the number of I/O at a reasonable pitch on a standard layout so that memory from multiple sources can be interchanged without a board redesign. Most fast SRAM devices today are already in flip-chip form, but within a BGA. The wafer CSP potentially eliminates the cost and electrical limitation of this flip-chip package. At issue is the reliability of the relatively small solder balls between the silicon and the PCB.

One approach developed by FormFactor is called MOST (MicroSpring On Silicon Technology). The MicroSprings are formed on the die while still in wafer form and serve double duty as test access points to the die as well as compliant standoffs that can be soldered to the board. Whether this approach is favored over the many others being considered for fast memory packaging remains to be seen. However, both Hyundai Electronics Industries Co. Ltd. in Korea and Infineon Technologies AG, Munich, Germany, have licensed this technology for their DDR memory die.

One proven technology that addresses the reliability of large memory devices is the post technology that provides some level of standoff and strain relief between the die and the substrate, rather like IBM Corp.'s column grid arrays on a smaller scale. Fujitsu Ltd. has been the principal proponent of this approach and Casio Inc.'s Wrist Watch Camera uses this technology in production.

Lower Leadcount Devices

Wafer CSP technology is particularly suited to low leadcount devices of less than 30 I/O. These include microcontrollers, temperature sensors, A to D converters, regulators, op amps, reference die, small digital signal processors, and very small memory devices.

The major users of wafer CSPs are companies like Dallas Semiconductor, National Semiconductor, and others who have very small die going into applications ranging from mobile phones to temperature sensors. Volumes are just ramping today, but could amount to significant volume production for these low leadcount devices. Handling and placing of these die is similar to other surface-mount packages (although they are quite small) and most of the smaller die do not require underfill for a reliable assembly.