Virata Adopts Sequence Design's Watt Watcher

Electronic News, Jan 29, 2001 by Gale Morrison

SANTA CLARA, CALIF.-BASED Sequence Design Inc. reported today that Virata Corp., also of Santa Clara, will deploy Sequence's Watt Watcher power analysis and optimization software on its broadband communications ICs.

After a long evaluation, Virata (nasdaq: VRTA) chose the Sequence tool set based on its support for register transfer level design flows, Sequence said. Virata will use the methodology to reduce chip power requirements in the development of symmetric digital subscriber loop communications processors.

"Silicon integration is a key driver of the digital communications buildout. As more advanced processing goes into larger and faster chips, power requirements explode," said Man Mohan, vice president of engineering at Virata.

"In practice, this means two things for design teams. First, power issues must be addressed early in the design cycle, and second, our tools and methodologies must support chip designs containing tens of millions of transistors. Sequence's Cool-by-Design approach is the only one we've seen that scales to the complexity of modern communications IC's."