Design for System-on-a-Programmable Chip

Electronic News, Feb 5, 2001 by David Greenfield

Advances in PLD size, speed and the accessibility of easy-to-use embedded processor cores and other intellectual property (IP) by themselves are not sufficient to enable system-on-a-programmable-chip (SOPC) design. It takes a clearly architected system-level methodology dealing with system-level complexity to deliver the time-to-market benefits that PLD technology brings.

Use of IP is now prevalent in high-density devices. While customers have used bus-interface functions and DSP functions for several years, three fundamental changes have recently emerged. First, application-specific compilers now deliver tremendous functionality and flexibility for IP. A new finite impulse response (FIR) filter compiler, for example, enables design of a filter with any number of taps and includes a built-in coefficient generator supporting coefficient widths from 4 bits to 32 bits of precision. The FIR compiler also supports decimation and interpolation options as well as serial and parallel arithmetic options. The result is a filter optimized for the exact performance and area requirements of a user, one that can also be easily modified and reevaluated to accommodate changing system requirements.

The second important shift in enhancing the design methodology involves the interfaces now provided to industry-standard tools. This FIR compiler, for example, now also generates MATLAB, Simulink, VHDL and Verilog HDL simulation models, enabling tighter links with powerful tools. Similar application compilers are emerging to support DSP applications like Reed-Solomon error-correction.

The third significant shift involving IP is the emergence of embedded processors optimized for PLDs. It's only with high-performance processors that the true potential of SOPC design capability is really possible. In a perfect world, a designer would simply generate C-code to embody the system specification and the tools would be smart enough to partition some algorithms in the embedded processor and synthesize logic for the remaining algorithms. Unfortunately, the tools are not yet this sophisticated. Integrating embedded processors within PLDs expose the designer to a plethora of new complexities. The new design methodology must address issues like modeling, integrating processor and PLD design entry and intelligently developing bus-interface elements to optimize system performance.

It's not just the IP elements of the design methodology that are changing. In many other ways the design methodology is closely aligning to the existing ASIC methodology. Design methodology shifts generally either occur because the new tools elevate system performance or because they provide productivity gains to shorten the design cycle. C-design and behavioral-synthesis tools offer promise of shortening design cycles. The challenge today with these productivity-enhancing tools is the question of whether a higher level of abstraction can create comparable performance (to the existing HDL methodology). Where ASIC technology often provides high excess performance (at the cost of flexibility and time-to-market), PLD customers generally want all the performance the PLD can provide. These productivity-enhancing tools will only be practical if they solve this abstraction-performance trade-off in a way that delivers optimum performance. If and when they do become viable, then formal verification also becomes viabl e in the PLD space.

One of the main advantages of using PLDs is that they provide a hardware platform on which it's possible to perform software development, modeling, system-level simulation and coverification very early in the design process. Getting a solution into silicon early in the process is only an advantage if it actually enables an efficient system-level debug process. First-generation debug products enabled visibility of all internal design nodes, while running the device at full system speeds. Look to future enhancements that provide this same visibility back to the original HDL source and enable fast turnaround to view additional nodes.

PLD tools must further evolve and leverage the benefits of research and development advancements of the EDA industry. While device complexity will always increase, the design methodology must deliver productivity gains by shortening the design process without compromising device performance. If successful, this technology will enable PLD-based products to encroach into traditional embedded processor markets and further accelerate the decline of the gate-array market.

David Greenfield is the director of development tools marketing at Altera Corp., based in San Jose.