Growth for semi packaging lithography - Commentary - Column

Electronic News, Feb 25, 2002 by Jim Walker

THERE IS NO DOUBT THAT advanced packaging lithography is a hot market today, as it is the only growing market in the back-end area. However, contrary to some beliefs, the use of photolithography technology in the semiconductor packaging area is not a new development.

For over 35 years, the "back end" (as it is often called) has been using photolithography in various forms for flip chip packaging. Developed in the middle 1960s, IBM pioneered use of this technology for producing "bumped" wafers. The resulting singulated die was then "flipped" directly onto the substrate (ceramic) and connected via solder bumps. Lithography was used to create the bump metallization structure of the bonding pad on the die. Since the exposed bonding pad on the die was made of aluminum, attaching solder directly to the aluminum presented some adhesion and reliability challenges. Thus a protective "cap" of deposited adhesive and barrier metals was created before attaching the final solder bump. It was this underbump metallization that helped enhance the reliability of the die and subsequent solder-joint to the substrate.

As the customer demand for smaller, thinner, and lighter products continues, it has driven the packaging technologist to develop and expand into flip chip and flip chip-like array packages. Flip chip interconnect is the lowest profile and most speed-efficient packaging technology. Bond pads can be placed throughout the die, not just on the periphery as in other packaging processes, so the die can be shrunk smaller while containing increased I/O. However, utilization of this array concept limits the full use of the main packaging interconnect technology used today: that of wirebonding.

Now, driven by market need, flip chip today has progressed beyond the traditional IBM Corp. C4 flip chip processes mentioned above. No longer dependent upon high-temperature melting (290 C), high lead content solder, flip chip and solder bumping technologies for chip scale (CSP) and wafer-level packages (WLP) have been developed and are becoming mainstream. Thus the increased interest in photolithography for semiconductor packaging and assembly.

Wafer-level packaging may be defined as wafers where all packaging and interconnection processes take place in wafer format prior to dicing or singulation. There is no subsequent molding or attachment to a "mini" substrate. As such, wafer-level packaging utilizes processes commonly found in manufacturing's front-end (wafer fab). These include film deposition, photolithography, electroplating, solvent resist stripping and metal etching. Therefore, for solder bumping and wafer-level redistribution techniques, lithography is a key element. This will become even more apparent as the move to 300mm-wafer fabrication continues.

One of the challenges facing the photolithography portion of the bumping process is the technology/equipment to use. Does one use contact proximity imaging or step-and-repeat? Each has its own strengths and weaknesses. Yield loss, resolution, automation and cost of ownership are just a few of the differentiating factors. These may become more pronounced as the 300mm market grows. And there's always the possibility another process or piece of equipment may be developed that fills the expanding market.

Thus, the technology innovations of wafer-level packaging and flip chip processing has resulted in the development and growth of equipment for this emerging technology.

The equipment manufactured and sold for packaging lithography was the only bright spot in the packaging/assembly market over the past year. The preliminary estimate for the backend lithography equipment market in the year 2001 was $65 million, representing a growth of 5.1 percent over the previous year. This follows a stellar growth performance in the year 2000 of $61.8 million, which was up over 260 percent from 1999. Now as the year 2002 is under-way, Dataquest believes the market for packaging lithography will grow at a much faster rate again, up 26 percent to $82 million.

Jim Walker is principal analyst for packaging and assembly at Gartner Dataquest Inc.