LSI adds 3 ASIC families:; up to 600,000 gates for gate arrays, standard cells and embedded controls

Electronic News, April 6, 1992

Up to 600,000 gates for gate arrays, standard cells and embedded controls

MILPITAS, Calif. -- LSI Logic Corp. has introduced three new families of application-specific ICs (ASICs) comprised of gate arrays, standard cells and embedded arrays that offer up to 600,000 usable gates.

Because of the high integration, complete PC chipsets with cache memory can now be implemented in a single ASIC, said Todd Scott, product line manager. Targeted applications include data processing, telecommunications, consumer and military applications.

LSI was able to achieve the higher density by using a 0.6-micron CMOS silicon gate process. The new families can accommodate designs using either 3V or 5V power supplies. "This is our last process for 5 volts, because in geometries below 0.6-micron the transistors get too fragile and require lower voltages," Mr. Scott said.

The gate array family, LCA300K, consists of 14 master slices from 10,000 to 500,000 usable gates. Mr. Scott said the use of a cell-based design tool called a hierarchical block compiler helps achieve the high integration of the arrays.

The LCA300K family is said to offer 215-picosecond gate delays and operating frequencies of over 75MHz. Memory capability reaches 96Kbit of static RAM and 385Kb of ROM, each comprising only half the die, Mr. Scott said. The gate arrays also are LSI's first incorporating pseudo-ECL I/Os and termination resistors for systems with special interface and termination requirements.

The cell-based LCB300K family features up to 600,000 used gates. A single die can accommodate 200,000 gates, 512Kb of SRAM and 1 megabit of ROM.

The embedded array family, LEA300K, is said to allow designers to combine the performance and density of cell-based devices with the fast turnaround of gate arrays by embedding the LCB300K cell-based memory and complex functions in its core.

The LEA300K is not dependent on gate array die sizes, according to Mr. Scott. Previously, embedded array devices were based on fixed-frame gate array master slices, he said. When the integration capability of the master slice was used up, the design had to migrate to the next available die size, resulting in higher prices. The new family offers incremental die size increases to accommodate increases in design complexity.

Mr. Scott said each type of ASIC has its own advantages, with gate arrays offering fast prototype and production deliveries, while cell-based ASICs have the highest integration potential and are most economical for high-volume production. Embedded arrays have gate array prototype turns and offer substantial increases in functionality, he said.

LSI Logic is offering the ASICs in both two- and three-layer metal, depending on the density required.

The 300K families offer substantial improvements over LSI's earlier 100K and 200K families, but the company does not plan to immediately withdraw those earlier designs. "We'll continue to book designs for them for the next 12 to 14 months," Mr. Scott said. "But it's inevitable that the 300K will supplant them both."

Production shipments of the new ASICs are scheduled for the fourth quarter. Non-recurring engineering charges start at $30,000.

The new ASICs are suitable for a wide variety of applications, he said. In consumer, they are aimed at video cassette recorders, high-definition television sets, cellular phones, and other uses. In data processing, they can be used at all levels, from the palmtop computer to the supercomputer, he said.

The new families are also aimed at high-speed communications, to conform to emerging standards such as FDDI, SONET and ISDN. Other markets include medical electronics and industrial controls.

Mr. Scott said the company was particularly emphasizing its cell-based family.