SGS-Thomson, Philips eye French 8-inch front-end venture; prototype line may convert to full production

Electronic News, April 27, 1992 by J. Robert Lineback

PARIS -- SGS-Thomson Microelectronics is negotiating with Philips Semiconductor International to transform a pilot eight-inch wafer facility near Grenoble, France, into a full-production joint venture.

SGS-Thomson and Philips, which last week formally agreed to collaborate on the development of a 0.5-micron CMOS logic process, will center their activity at the SGS-Thomson pilot plant, called Grenoble 92, in Crolles. Construction of the plant was launched in 1989 by SGS-Thomson and the French telecommunications research institute, known as CNET.

With Philips now involve in the 0.5-micron project, the Crolles facility is being suitably equipped for the joint R&D effort as well as initial pilot production of 1,000 eight-inch wafers a month. If fully equipped, however, the front-end would be able to process 5,000 eight-inch wafers a week, according to SGS-Thomson president and chief executive Pasquale Pistorio, who indicated his company would welcome Philips' participation in such a costly expansion.

Philips will decide whether to expand its involvement at the Crolles plant after the first prototype devices are produced on the pilot line in 1994, said Heinz W. Hagmeister, chairman and chief executive of Philips' semi-conductor subsidiary. One alternative, he said, would be to transfer the jointly-developed process to Philips' Nijmegen plant in the Netherlands.

Whatever Philips decides, Mr. Pistorio vowed that the Crolles plant would eventually be equipped to become a "European center of manufacturing science" and a major silicon foundry. He said that a decision to move ahead with full production at Crolles would be governed by user demand, but a choice would have to be made by 1994 to have the facility ready to serve high-volume markets in the second half of the 1990s.

The project's importance goes far beyond SGS-Thomson and Philips, according to Mr. Pistorio, who has become one of Europe's most vocal advocates of pan-European electronics cooperation. "It is not just Philips and SGS-Thomson who will benefit from the center at Crolles. The results of our joint R&D activities will be placed, where possible, at the disposal of other European companies," he said. "We are prepared to work together with both users and producers of semiconductors to develop the systems on silicon that will eventually allow us (Europeans) to meet the Japanese challenge in electronics."

When asked how technology would be made available, Mr. Pistorio indicated through individual agreements struck by Philips and SGS-Thomson as well as possible inclusion of other firms in the project once the 0.5-micron technology is running products through the pilot line. Eventually, Mr. Pistorio hopes to turn the facility into a large silicon foundry for Europe.

At an estimated cost of $100 million to increase wafer throughput by 1,000 wafers a week, a total investment of approximately $500 million would be needed to fully equip the plant, said Mr. Pistorio.

The companies plan to apply for European Community and local government grants to support projects within the alliance. Although no formal proposal has been submitted to the EC's Joint European Submicron Silicon Initiative (JESSI), both Messrs. Pistorio and Hagmeister said the Philips/SGS-Thomson alliance has gained favorable responses from European leaders.

"No question, we will apply for funds on a project-by-project basis. This, we believe, is a good project for Europe's microelectronics industry," said Mr. Pistorio, who added that despite some concerns in Europe, he believes the Crolles project will complement rather than compete with JESSI.

The signing of the technology alliance last week brings to fruition an agreement in principle announced by Philips and SGS-Thomson late last year (EN, Nov. 25, 1991). Under the terms of the accord, Philips and SGS-Thomson will create a common 0.5-micron process for logic devices, including application specific standard products (ASSPs) and integrated circuits (ASICs). Telecommunications, consumer and automotive applications are expected to be major areas of focus.

The pact also includes the creation of common design rules and cell libraries for the 0.5-micron CMOS technology, which is scheduled to be ready for products by the end of 1993.

Both Philips and SGS-Thomson plan to use the Crolles pilot line to develop their first products in the new technology. Philips is likely to select a high-volume IC targeted for consumer product applications as its first part produced in the 0.5-micron CMOS technology, said Mr. Hagmeister.

"It will probably be for digital compact cassettes." he suggested. "This is a good candidate because the market volumes increase very quickly."

SGS-Thomson is planning to take a much different path in first using the new technology. Aiming for high performance and lower volumes, SGS-Thomson will first use the 0.5-micron process to make a large sea-of-gate array, with as many as 400,000 total gates, said Piero Martinotti, vice president of corporate strategic planning. The array will use three levels of metal for interconnection and feature embedded function blocks, such as RAM.