CAE software: OVI's multilingual models

Electronic News, May 4, 1992 by Daniel Holden

When Bruce Bourbon, chairman of Open Verilog International (OVI), said recently that the group was looking into ways to achieve interoperability between design language models, including those written in Verilog and in the VHSIC hardware description language (VHDL), OVI members clamored for a chance to participate in the process.

But what appeared to be an open discussion of a new idea now looks more like a months-old backroom deal that spilled uncontrollably out onto the streets. And the primary deal makers are Cadence Design Systems -- under the auspices of OVI -- and VHDL International.

Originally, Mr. Bourbon said OVI was discussing the idea with representatives of VHDL International and the CAD Framework Initiative (CFI). VHDL International's president, Robert Blair, confirmed that he and Mr. Bourbon have talked of the idea since March. But Andy Graham, president of CFI, said his group had not been contacted at all.

Executives at Cadence explained the situation by acknowledging that there is more strategy to the plan than was originally revealed.

"OVI has been trying very hard to initiate something with VHDL International," said Venktesh Shukla, manager of strategic marketing at Cadence and a former program manager for OVI. "We've not been getting as much cooperation as we would have hoped.

"We've been trying for the last six to nine months to form a joint technical committee between OVI and VI, because ultimately that's what users want. If that doesn't work, we'll fall back on CFI."

Indeed, said Mr. Shukla, both the VHDL group and OVI will eventually have to work with CFI to develop a common data representation standard to allow users to store and access information. CFI is working on just such a standard at the netlist level; OVI and VHDL International are negotiating interoperability at the behavioral level.

The driving issue, from a user's standpoint, is developing interoperability between VHDL and Verilog models for simulation and synthesis purposes. Without interoperability, simulation of models written in different languages becomes a complex problem, impacting heavily on time to market.

Mr. Blair said his industry group is open to the interoperability idea.

"We agreed that it makes a lot of sense," said Mr. Blair. "VI very much recognizes that other HDLs exist, and that the right degree of interface and interoperability is appropriate."

Mr. Blair said VHDL International acknowledges that, "There are a lot of companies that are committed to Verilog, and that's not going to change overnight. You can't bulldog Verilog out."

Similarly, Mr. Blair added, "Cadence recognized that stonewalling VHDL isn't going to make VHDL go away. And overpitching Verilog isn't going to make VHDL go away, either. There has to be coexistence."

So why all the pushing and shoving?

The details are not clear, but the major sticking point appears to be OVI's stated goal of getting Verilog approved as an Institute of Electronic and Electrical Engineers (IEEE) standard (VHDL already is an IEEE standard). Mr. Blair said VHDL International does not support that effort.

"We believe having VHDL as the standard is the right thing for our industry as a whole. It's very neutral, it doesn't have the hidden attachment to it that some languages have," he said, alluding to the fact that Verilog was once a proprietary product of Cadence's.

"I think it would be a mistake for the end user to have that degree of apparent standardization to choose from," said Mr. Blair, adding that standardization under a single language, namely VHDL, "will generate a larger market for everybody to play in."

Nevertheless, he said he recognizes that OVI might not back down from its goal of becoming a standard. And that means greater competition between the two languages -- and tougher talk at the bargaining table.