Cadence snubs VHDL International, pushes Verilog for ASIC design

Electronic News, June 15, 1992 by Daniel Holden

ANAHEIM--Cadence Design Systems brushed aside the advice of VHDL International executives and instead announced a unilateral initiative to use Verilog practices as the standard for application specific integrated circuit (ASIC) design in the VHSIC hardware description language (VHDL).

The standard practices idea in itself was not new--Cadence president Joseph B. Costello made the same proposal at the VHDL International Users Forum in Scottsdale, Ariz., one month ago (EN, May 11)--but his whipping up of support for the initiative was definitely greeted with consternation by some VHDL proponents.

Cadence executives said they formulated the announcement in the two weeks before the Design Automation Conference (DAC) here. In the week immediately preceding the conference, Cadence gathered a series of endorsements from such electronic design automation (EDA) users as Alcatel NV, Bell-Northern Research, Ericsson Telecom AB, Harris Semiconductor, National Semiconductor, NEC Electronics Inc., Oki Semiconductor, Texas Instruments, Toshiba and Xilinx.

Several of these companies said they expedited their endorsement process to get behind the initiative, many in as few as three days. Mr. Costello said several other companies, including Motorola and LSI Logic, expressed support for the initiative, but could not get approval to endorse the project in time for the DAC announcement.

Under the initiative, Cadence will submit a proposal for the adoption of Verilog-standard

ASIC modeling practices as the standard for similar capabilities in the VHDL language. Cadence said the adoption of the Verilog standard practices would expedite the availability in VHDL of about 140 libraries from 30 ASIC vendors, representing some $1 billion in development resources. All the libraries are written in Verilog.

"The users have clearly stated their preference," said Mr. Costello. "They want to get on with it. They want to use VHDL, and they want to support standard practices."

Mr. Costello said Cadence is not trying to create a new standards body or organization. "The goal is to build support around this initiative, and then to find a home for it," he said, adding that home could be the VHDL International (VI) group, the Open Verilog International group or the IEEE.

Cadence said the company "will serve as the initial point of coordination for the initiative, but expects ultimate control and responsibility to be turned over to a user-driven organization." Plans for a formal proposal covering the Verilog-standard ASIC modeling practices will be completed in the third quarter, according to the company.

While Cadence clearly demonstrated a prodigious amount of support, not everyone involved is happy with the idea. Officials at VHDL International said they support any initiative which serves to promote VHDL as the industry standard language, but they disagreed that the Verilog standard practices are necessarily the appropriate solution for VHDL modeling.

"To want to base VHDL modeling on Verilog is a bit difficult for some of our people to take," said Robert N. Blair, president of VI. "Incorporating Verilog into VHDL, maybe; but not a Verilog modeling standard."

Mr. Blair said it is "Somewhat inconsistent with VI's objectives" to use the Verilog standard practices as the basis for VHDL modeling. "VI does not endorse individual companies or one company's products. That's not consistent with our idea of an industry standard objective."

Mr. Blair said he is particularly upset with the methods of Cadence in making the announcement. "We tried very hard last week to soften their wording. There were things they wanted to say that we just couldn't go along with," said Mr. Blair.

Still, Mr. Blair said he was hopeful the uproar would subside in time. Indeed, VHDL International later issued a statement saying the organization supports a proposal for "a standard for VHDL ASIC models that includes the currently used standard practices of Verilog HDL." The statement said the organization is also reviewing a proposal from Mentor Graphics Corp., as well as the Electronic Industries Association (EIA) 567 Modeling Standards Specification for VHDL. VI said it expects the standardization of modeling to be one of the two major projects for the current year. "All of those environments need to be part of the future standard,' said Mr. Blair.

Cadence officials later said that all the Verilog standard practices in the proposal are currently in the public domain through Open Verilog International. Mr. Costello said his conversations with VHDL users lead him to believe that the user community does not want to wait for VHDL International to come up with a standard.

Still, some insiders said an important reason for concern is Cadence's unabashed claim that it intends to become the industry leader in both Verilog and VHDL.

In an earlier meeting with the press and industry analysts, Mr. Costello said he wants to see Cadence become the undisputed leader in both VHDL and Verilog-based design.