Sparc group boosts 64-bit performance

Electronic News, June 22, 1992 by Jonathan Cassell

SAN FRANCISCO -- In a bid to remain competitive with rival RISC architectures, the consortium grouped around Sun's Sparc architecture last week

unveiled a new 64-bit specification that boosts high-end performance and remedies several perceived limitations of the processor.

The so-called Version 9 specification unveiled by Sparc International thus appears to be another effort to counter the momentum generated by Hewlett-Packard's PA-RISC and IBM's Power architectures, which have outstripped Sparc's performance at the workstation level, and Digital Equipment Corp.'s planned Alpha processor, a 64-bit architecture that promises to beat Sparc at the high end. Version 9 also includes several fault-tolerant features and is claimed to provide greater support for advanced compiler optimizations, multiprocessing, superscalar processors and sophisticated operating systems.

Sparc International "really needed to do this to compete with Alpha, as well as with current PA-RISC chips from HP," said Dataquest analyst Lisa Thorell. The Sparc group wouldn't provide specific performance levels, but Ms. Thorell said Version 9 has at least the potential to exceed PA-RISC and Alpha. She believes the first Version 9 processor will make its appearance by year-end.

Texas Instruments, which had a representative on the Version 9 architecture committee, will make available a 64-bit Sparc to Sun at an unspecified time in the future, a TI spokeswoman said. Cypress Semiconductor, also represented on the committee, could make Version 9 a priority after being beaten by TI in the competition to fabricate the initial processor for Sun's recently unveiled SparcStation 10 line (EN, May 11), but the firm did not respond to a request for comment by press time.

Version 9 for the first time enables Sparc to perform simultaneous processes through the addition of fast context switching. The new version also doubles the number of double-precision floating point registers to 32; doubles the number of quad-precision floating point registers to 16; and adds three more floating-point condition registers for a total of four.

Other upgrades include prefetching data and instructions, a Tick register, and support for misaligned data, speculative loads and conditional moves. The operating system has been completely redesigned to support new privileged registers and structure, new privileged instructions, microkernel design, lightweight threads and objectoriented software.

Version 9 processors will have full binary compatibility with current Sparc software, but Version 8 applications will have to be recompiled to take advantage of new features, said Dave Ditzel, chairman of the Sparc architecture committee and director of advanced systems at Sun Microsystems Inc.

While Sparc officials said Version 9 would be fully scalable, fault-tolerant features such as the compare-and-swap instruction and multiple levels of stacked traps make it more attractive to such mainframe and supercomputer builders as Amdahl and Fujitsu, which are also represented on the committee.

A start-up company, Hal Computer Systems Inc., claimed to have been developing its own Version 9 Sparc over the past year-and-a-half using "advanced CMOS technology," said its chief executive, Andrew Heller, who would not provide further details.