Intel shifts i860 RISC from CPUs

Electronic News, August 3, 1992 by Adam Greenberg

WASHINGTON--Intel last week acknowledged that it is shifting the i860 RISC microprocessor away from merchant central processor bids, a fate that was cemented recently after a quartet of system vendors showed no signs of long-term commitments to the part as a CPU.

Intel's new CISC-only merchant CPU direction was outlined by Paul Otellini, vice president and general manager of the Microprocessor Products group, at the CTOS Americas conference here. Mr. Otellini delivered a keynote to users of the Unisys client/server architecture, which specifies Intel x86 workstations, titled "RISC Versus CISC and Other Fairy Tales."

The executive formalized the i860's status after his address, saying Intel is "not going to drive it as a CPU. There's a couple of people like Stratus that use it as a standard reprogrammable deal, (but) it's probably shipping the most units into video accelerator, graphics accelerator capabilities."

Asked when Intel decided to reposition the i860, Mr. Otellini said "The market makes those decisions. No one bought it" as a CPU. Intel in late 1990 began downplaying its i860 marketing effort in the workstation CPU area (EN, Jan. 28, 1991).

Since May, four i860 CPU customers have either designed the component out of future generations or withdrawn i860 processors from the market. These include parallel processor vendor Alliant Computer, which suspended all operations except service and add-on sales as part of a Chapter 11 filing (EN, June 1); Oki Electric, which closed its U.S. workstation unit due to poor sales (EN, May 18); Stratus Computer, which decided to base next-generation fault-tolerant processors on Hewlett-Packard's PA-RISC (EN, June 29); and IBM, which plans to eventually base its Power Visualization server on its own Power/RISC unit (EN, Data Topics, July 27).

"The lesson we learned with the 860 is two architectures is one too many" for the CPU market, Mr. Otellini said. "$2 billion a year to support one architecture, how can you make a second architecture successful?" he asked, referring to Intel's projected 1992 expenditures on machinery and equipment, land and buildings and R&D.

In his keynote address, Mr. Otellini used a glimpse at Intel's future P6 and P7 generations to back up a claim that CISC designs are capable of outperforming RISC processors. The P6 and P7 units are expected to integrate speech recognition character recognition and video capabilities on a single CPU, with P7 expected to reach the 12 million transistor mark before the turn of the century.

Further down the road, a more than thirtyfold increase in the P5's three-million-transistor capacity is envisioned. "It's very conceivable that good old silicon can give us, on CMOS technology, right around 100 million transistors," Mr. Otellini said, adding that the battle between RISC and CISC architectures "will all come down to execution--the ability to capitalize on an idea."

Intel envisions building millions of P5 and P6 units by 1994, Mr. Otellini said, with a 0.6-micron process expected to be in production next year on the 486 and P5. Mr. Otellini would not say which geometry would follow the 0.6-micron linewidth, but he noted that Intel is "actively working on the technology and we expect to deploy it in the '95-'96 timeframe for production."

The executive also was reluctant to say which MPU initially will be fabricated in the 0.6-micron process. "It depends on where the center of the market for performance is," he said. "The center of the market for performance for the 486, and there's a bunch of stuff at 20-25MHz and a bunch of stuff from 50-66MHz. I think a year from now that will move to 50-66 as being the center of the market with 180 at the very high end and 33-50 at the low end."

On the subject of P5's introduction delay (EN, July 27), Mr. Otellini denied Intel is trying to buy time to squeeze more profits out of its 486 parts. Despite earlier price cuts at the line's low end (EN, May 18), Intel enjoys relatively little competition in the 486 market compared to the number of entrants in the price-sensitive 386 segment.

"If I was nefarious I'd introduce the P5 tomorrow and raise the bar," Mr. Otellini said. "The worst thing I could do is introduce the P5 when AMD is still shipping 386s," he added in reference to a recent jury decision that is forcing 386 competitor Advanced Micro Devices to re-engineer its 486 microcode (EN, June 22).

Mr. Otellini said Intel has more system designers committed to P5 than were initially focused on the 386 or 486, adding that "everyone except Sun, MIPS and SGI" has committed to using the new part. He maintained that no system vendors were left in a lurch by the delay, which is aimed at placing P5's unveiling and volume production ramp within the same quarter. "Historically we'd introduce it, we'd show three parts that wiggle on stage and we'd ramp six months later," Mr. Otellini noted.

The executive would not say which system vendors would be first to market with P5 platforms, but noted in his CTOS address that Unisys has committed to use Intel MPUs for all future product developments except high-end mainframes.