Triple layer metal scheme still waits for ASIC stardom

Electronic News, August 3, 1992 by Richard McCausland

Several years after emerging as a commercially viable interconnect scheme for application specific integrated circuits (ASICs), triple layer metal continues to retain its "Just in Case" status among existing conductive path methods.

"Triple layer metal as an option available to provide flexibility is more important to the supplier than to the customer," said Harold Blomquist, vice president of sales for American Microsystems Inc.

"We first try to do the routing with double layer" when presented with a new gate array design, said Nitin Deo, applications engineering manager for Fujitsu Microelectronics. "You can try everything in double metal." Asked about end-user preference, he replied "The customers haven't really said one way or the other."

By most accounts, triple layer metal (TLM) doesn't become a real design consideration until the gate density exceeds at least 50,000. According to Mr. Blomquist, however, the average gate count for designs from AMI is currently 15,000 to 20,000.

"I don't see anything over the next several years that's going to drive the average gate count over 50,000 gates," Mr. Blomquist said. "There's going to be for almost forever a lot of need for random logic, and as long as that continues to prevail, there will be a lot of low-level logic applications where TLM will not really be a factor."

He suggested that when gate densities reach 100,000, TLM becomes a "strategically critical process technology," but added "It really has a long way to go. The factory folks sure don't want to run it if they don't have to."

With triple layer metal, it is possible to do routing in levels 2 and 3, which are independent of the internal layout. The interconnections can then be laid directly over the incorporated cells, like a highway overpass, which allows for greater packing density.

Impeding a wider acceptance of TLM, however, are increasingly smaller line width production processes. "With the technologies that we have today, particularly at 0.5 micron, we're getting pad-limited," and so a customer is "not saving anything" in usable gates by adopting TLM rather than a double-layer approach, said Steve McMinn, in charge of ASIC marketing for Toshiba's Semiconductor group.

Nor is that situation likely to change anytime soon. Jeff Hendy, director of new business development for VLSI Technology, observed "As you go to wider bus width--from 8 to 16 to 32 bits--more and more designs tend to get I/O-limited. It doesn't make any sense to go to TLM; you don't add any gates." He further contended "The number of I/O-limited designs is increasing as a percentage of total designs."

For now, "Where triple layer really shines is where the size of the die is set by the core," noted David Pivin, strategic planning manager for Motorola. All logic functions except I/O (input/output) buffers are core logic.

It's been five years since Motorola introduced its High Density CMOS series of 1-milcron TLM arrays capable of achieving 75 percent utilization in densities ranging from 6,000 to over 100,000 gates. The series employs a channelless sea-of-gates architecture.

More recently, in April, Motorola brought out the H4C Series of arrays, which use triple layer metal routing and combine densities up to 318,000 gates with user-configurable RAMs up to 256K bits. The incorporated transistors employ a 0.7-micron effective channel length process. Typical gate utilization is 70 percent in most applications.

With double layer, "There is a slight advantage" in turn-around time over triple layer, Mr. Pivin acknowledged, "but I don't think it impacts the business." For TLM, "Turnaround time on average is three to four weeks. In a rush, we can do it in two weeks or less."

Mr. McMinn of Toshiba noted "I wouldn't say we have what you would call significant volumes in triple metal," although "We do quote triple metal for quite a number of customers, particularly when they have a granularity problem."

The market for TLM is still developing, he suggested. "It will get cheaper in the production environment as it gets more volume behind it."

"More and more of our revenues are coming from triple layer metal designs," noted Brian Bennett, strategic marketing manager for high performance ASICs at Texas Instruments. He cautioned, though, "It will be some time before TLM is mainstream in production."

Its attraction, obviously, is "You can get much better silicon utilization in area terms. You also have shorter routes; you can go point to point without going down through the vias and going around."

But its acceptance has largely been centered around makers of mainframes, telecom equipment and, to a lesser degree, high-end personal computers, according to Mr. Bennett. Referring to TLM, he said "It's a response the (semi-conductor) industry has made to customer requests for high density and performance. In time, it will gravitate down."

For now, it's largely unnecessary for low-end systems. "You're under cost pressure. A double layer metal option is a good option to have."