Triple layer metal scheme still waits for ASIC stardom

Electronic News, August 3, 1992 by Richard McCausland

"Triple metal for us has been very much a core technology," Mr. Dichter said. "In general, more and more triple-layer devices will be available just because you need the routing density." He added "There are performance considerations to selling the smallest die, which means going with triple metal."

VLSI Technology last year introduced its FlexArray design capability based on 0.8-micron (drawn channel length, with an effective channel length of 0.7 micron) CMOS libraries that enable designers to combine gate array and cell-based structures on a single chip. The VGC453 is a triple-metal option for the two-layer metal VGC450.

The company's Mr. Hendy observed "All of our libraries work with double or triple layer metal; that's the only way to run it." Still, the number of TLM designs done by VLSI is "not a huge number."

It's been at least five years since LSI Logic developed TLM interconnect technology to produce its LCA100K HCMOS arrays with 100,000 usable gates. More recently, in April, the company brought out the LCA300K Compacted Array series, LCB300K Cell-Based ASICs and LEA300K Embedded Array ASICs, all of which offer up to 600,000 used gates and I/O counts greater than 800. These newer products are based on a 0.6-micron drawn (0.45-micron effective) CMOS silicon gate process.

John Daane, product marketing manager for ASICs, commented "All the products we offer have the option of two or three layers. We gage it at around 50,000 gates to make the crossover from double to triple layer metal."