Transition: from performance to economics

Electronic News, Oct 5, 1992 by James T. Healy

Costs to manufacture and test semiconductors have moved upward at a mind-boggling rate. At the same time the complexity of the device has increased at the same rapid pace while the average selling price (ASP) of these very same devices has plummeted. This has put tremendous pressure on device margins and hence on semiconductor profits.

Soon something must give. Since it is unlikely that ASPs will rise soon, the cost of manufacturing must come down.

Testing is a major cost factor in the manufacturing of semiconductors, evolving from an "insurance policy" to a bounded operation over the past three decades.

In the 70s technical feasibility was the focus with major breakthroughs occurring in moving from manual to automatic testing at reasonable costs. In the 80s technical expansion drove the industry.

Performance was driving economics and engineering was driving production. Everyone wanted faster processes and higher performance, at any price. But in the 90s the reality of more intense competition, lower margins, and shorter times to market is breaking the paradigm. Economics is now driving the technology.

In a November trade press article the CEO of Teradyne said that customers are resisting paying for performance and that Teradyne will have to become a low-cost producer.

At a recent analyst conference, the CEO of Credence said that an ATE company could not be an effective cost leader if performance were comprised in order to reduce costs.

New and innovative ways must be discovered to reduce the cost of testing. Multi-site testing where two to eight devices are tested in parallel is one approach which will significantly increase tester throughput.

Using low-cost CMOS instead of expensive ECL in tester designs will greatly reduce the cost of both the tester and the testing environment.

CMOS designs can result in as much as a 90 percent reduction in both power and space requirements, thus dramatically increasing facilities throughput.

In a June memo to VLSI ATE vendors, Motorola added a new metric for comparing various tester and handler/prober costs. The "Test Floor Space Index" is the ratio of floor space required to the number of devices tested in a specified time period. A metric based on devices per watt of power is probably just around the corner.

Software is another ATE cost parameter that is being attacked. Some ATE companies have tried to reduce cost of ownership by relying on more sophisticated software packages. But users are reluctant to pay a premium since ATE software is dedicated to one ATE vendor's products or model.

The ATE purchaser may be better off relying on third party software houses like TSSI or Cadence to provide the interface to CAE systems.

To quote the president of Schlumberger Technologies, "We are serving a market that never appreciated the value of software." This may be the case, but if tester-independent software solutions were provided by the ATE manufacturers, the user would value the software and pay for it accordingly.

Software has little value once the user changes tester hardware platforms since it will not be compatible with the new platform or vendor, and change they must.

Intel is a case in point. Since its founding, Intel ATE has "metastasized" from in-house manufactured testers to equipment from Megatest, then from Fairchild, then Teradyne, then the 386 introduced in LTX/Trillium, and now from Schlumberger.

At a Semicon presentation in November 1991, Gordon Moore of Intel suggested the reason. He presented an "apparent" business model of semiconductor equipment, showing the development of "utter greed" in the transition from technology leader to market leader. This in turn leads to dissatisfied customers, since the supplier often feels no further need to listen. The customer then "bails out" and the supplier starts to lose market share. The supplier now either goes to an early grave or, driven by fear, reevaluates the situation and starts to listen again. This revives the relationship with the customer, but now greed and fear of bankruptcy are in balance.

The testing problem is bounded. We have transitioned from immature to mature markets, from unknown problems to known test requirements, from poor design-for-test to excellent CAD and DFT packages.

A more competitive maturing market demands low overhead. Semiconductor manufacturers must seek lower-cost hardware solutions where the performance needed for testing is balanced with the costs needed for the business. Performance alone is no longer the driving mechanism. Economics dominates.