Mentor links with ASIC vendors

Electronic News, Oct 5, 1992

WILSONVILLE, ORE.--Five ASIC and FPGA vendors will provide design kits to support Mentor Graphics' "top-down" design software. Participating in Mentor's new SmartStart marketing program are Fujitsu, LSI Logic, Mitsubishi, VLSI Technology and Xilinx.

Sun Microsystems is also involved in SmartStart, which will take in training, seminars, workshops and consulting services. Mentor is seeking more ASIC vendors for the program, which is tied into the Top Down Design-Solver suite of tools, and says it will have 50 additional design kits by year-end.

Mentor has formed an ASIC Vendor group in its bid to claim dominance in the ASIC design market (EN, Antenna, Sept. 28), which is also part of a corporate drive to focus on "critical customer programs" (EN, Aug. 31). It has set up "top-down design centers" at four locations in the U.S. and in Tokyo and Munich.

The design kits available in Q4 in North America will support Fujitsu's CG31 and CG21 gate arrays, LSI Logic's LCA 300K and LCA100K gate arrays, Mitsubishi's M6008X, M6007X, M6006X and M6005X gate arrays, VLSI Technology's VSC470 and VSC450 standard cells and VGC450 gate array and Xilinx' XC4000, XC3000 and XC2000 field programmable gate arrays. They all run on Sun and Hewlett-Packard workstations.

David Chen, Mentor's vice president of corporate marketing, emphasized that Top Down Design-Solver represents an integrated approach to advanced ASIC design. Drawing on the capabilities of the Falcon Framework and other Mentor tools, the Mentor design suite ensures that "What you spec is what you get," he said.

Mentor said it has received more than $10 million in orders for Design-Solver, and at least six ASICs have been produced with the software, including a fiber channel transmitter designed by Ancor which is said to have 273,000 "raw gates" and is implemented in a 0.7-micron CMOS process.

Design-Solver is immediately available on Sun Sparc platforms and on HP/Apollo 9000 Series 400 and 700 platforms, with pricing beginning at $135,000. The suite includes Design Architect for design entry, AutoLogic for synthesis, QuickSim II for mixed-level logic simulation and QuickPath for timing analysis. It also can include two new automatic test pattern generation (ATPG) tools, FlexTest and FastScan, which Mentor developed with CheckLogic Systems Inc. FlexTest works with AutoLogic to generate fault coverage test patterns with sequential, partial scan or full scan designs. FastScan provides more comprehensive ATPG tool for high-density, full scan designs. They are available on a stand-alone basis at slightly less than $100,000 for a network license.

Mentor is taking a more aggressive posture in marketing Top Down Design-Solver and related products, openly questioning the capabilities of competing products from Cadence Design Systems and Synopsys. Robert Mendes da Costa, director of marketing for Mentor's Design & Synthesis division, last week used a number of military metaphors in comparing the company's top-down software to the competition, saying "We're massing troops and crossing the border."

Mentor's presentation included a series of "questions to ask" Joseph Costello and Harvey Jones, the CEOs of Cadence and Synopsys, respectively, about their top-down software, covering such minutia as "How easy is it to model a 4th order polynomial using Cadence's new timing equations?" and "How is Synopsys going to address timing-driven, top-down design without floorplanning scheduled for development/delivery?"

Isadore Katz, Cadence's vice president of IC marketing, said his company modeled a 21st order polynomial in the course of developing ASIC Workbench, its latest ASIC design suite, which begins shipping this month. Regarding Design-Solver, he observed "Most of the packages and technologies are pretty much existing products." Addressing the list of questions for Mr. Costello, Mr. Katz said "The more important issue... is: Where is the market going?" The answer, he said, is not only in logic design methodology, but also in hardware description language-based design, "to brace the logical and physical gap."

Mr. Jones of Synopsys said that Design-Solver represented "a veneer of marketing on top of old technology, failed technology." Regarding the question addressed to him, he said "We are the only company with timing-driven analysis. We not only addressed it, we embedded it." Floorplanning, said Aart de Geus, Synopsys' chairman and senior vice president of marketing, is a method of overcoming "shortcomings of the place-and-route system."