Motorola signs NeoCAD as FPGA design partner

Electronic News, Feb 1, 1993

PHOENIX, ARIZ.--Motorola's semiconductor products sector said last week it signed an anticipated (Antenna, Jan. 25) four-year partnership with EDA vendor NeoCAD of Boulder, Colo., on software for the design of field programmable gate arrays (FPGAs). Meanwhile, industry insiders said Intel in mid-February will introduce similar FPGA design software, but it's unlikely to be linked to NeoCAD.

Under terms of the agreement with Motorola, NeoCAD will provide a complete design toolset for Motorola's new FPGA device family. Those tools will also serve as a core for supporting future devices from Motorola. NeoCAD said the tools developed for Motorola will use the company's existing interface and will be compatible with NeoCAD's other, device-independent modules. A new tool, FPGA Architect, allows critical trade-offs between software and silicon to be considered simultaneously.

Motorola said the tools will be available for shipment in July through its sales channels for about $6,000 in workstation and PC versions. NeoCAD's value-added reseller network will offer FPGA Foundry in support of the Motorola device. First samples of the silicon will be available in December 1993.

Motorola said customers are demanding timing-driven tools for high-end, critical FPGA designs, and it is confident its products will prove out in a device-independent design environment where it will compete with such vendors as NeoCAD partners Altera and Xilinx. Details of Intel's development are unclear; insiders suggest it involves similar FPGA design tools, but unlikely to involve NeoCAD.

NeoCAD president and CEO Amaury Piedra said the company has had discussions with other unidentified FPGA vendors. He noted, however, the broad-based EDA vendors, including Cadence and Mentor Graphics, "have been very amenable to dealing with us" rather than pursuing the market themselves.

"It's not a trival thing to put together the expertise in windows, graphics, timing, place-and-route, synthesis and the hierarchical data-base required," said Mr. Piedra. "It's a two-year task to put that all together. So by the time they have two architectures ready, we'll have 10."

Paul Butler, a principal engineer and scientist with Motorola's programmable logic products division, agreed, noting FPGA vendors "are not going to want to be limited by the tools they use. What the customers really want is a continuous EDA solution."

In another development, Motorola selected Integrated Silicon Systems (ISS), Research Triangle Park, N.C., to supply IC layout verification software at design facilities worldwide. Mike Jamiolkowski, ISS vice president of marketing, said the deal is worth several million dollars initially, with possible follow-on orders. Several Motorola locations had already bought ISS VeriCheck software independently; shipments on the company-wide order are beginning now and are to be completed by yearend, said Mr. Jamiolkowski.

Included in the buy are a layout rule checker to be sure devices meet process specifications; a layout-to-netlist comparator; an electrical rules checker and a layout parameter extractor for use in circuit analysis and simulation. The VeriView graphical debug environment is also being purchased.