Unisys improves CMOS with Motorola devices: remaps logic design

Electronic News, Sept 20, 1993 by Reinhardt Krause

BLUE BELL, PA.--Unisys last week took another big step in migrating its water-cooled, bipolar, ECL based mainframes to CMOS technology, remapping the instruction processor (IP) logic design of its high-end 2200/900 system onto Motorola's 0.8 micron H4C gate arrays.

The transformation to CMOS results in the 2200/500-which provides one-fourth the power of its flagship machine per IP but improves on the performance of Unisys' earlier CMOS endeavor, the 2200/400, by up to three times.

Although the transition to CMOS may involve some sacrifice in power--the 220 0/900 provides 40Mips/s per IP while the 2200/500 will run at 10 Mips/s--chip count was reduced from 197 in Unisys' 2200/900 system to 18 in the denser 300,000 gate CMOS packaging.

Unisys officials said that while some customers could cluster processors to gain the same type of performance as the 2200/900, the new CMOS implementation allows scalable mainframe performance in a rack-mounted office enviromnet. "We can drive down (from the 2200/900) to a different class of customer," said Curt Girod, vice president of program management, computer system group.

The starting price for the 2200/500 is $350,000 for a minimum configuration of one IP, one I/O processor, and 256MB of memory compared to several million dollars for the 2200/900. The first beta 2200/500 machine will ship this week, with volume production by December; Unisys claims to have $50 million in customer orders for the 2200/400.

IBM and other companies are also making the move from custom built mainframes to CMOS technology, because of the lower cost, space savings, and reduced power consumption that eliminates the need for water-cooled technology.

Each 2200/500 instruction processor is packaged as a 11 x 4-in. printed circuit board containing eighteen 591-pin CMOS ASICs. Jim Commander, 2200/500 development manager, said each ASIC includes embedded RAM as a first level cache.

Motorola, which now serves as a foundry for Unisys after its shuttered its own bipolar and CMOS plants, also contributed to the development of marcos enabling up to 95 percent of the 2200/900's logic equations to be directly mapped to the 2200/500 without reparitioning. "We were able to come to market very quickly with this," said Mr. Girod; the 2200/900 began shipping in volume last year.

Unisys described the 2200/500 as a close architectural kin to its 2200/900; the new CMOS-based machine implements the Extended Processing Architecture of the high-end mainframe as well as its block mux channel. AXP provides 54-bit virtual memory addressing and 36-bit real addressing. The 2200/500, likewise, has a maximum memory address of 256 million words. It uses 16Mbit DRAMs; Unisys did not provide the source.

With the 2200/500, Unisys is also improving significantly on its first try in implementing CMOS technology, the 2200/400. The 2200/400 was rolled out in 1989 and used Unisys' own 1.2 mircon CMOS, 30K gate technology. Using 1 Mbit memory chips and a 16 million word architecture it also had limited expandability. The 2200/400 was designed with 22 chips, but with a much less robust architectural scheme.

The 2200/500 comes a standard 19-inc. rack mounted system that can be configured with up to four processors, 1GB memory, and 900 ter-abytes of addressable data. When configured with Unisys' extended Processing Complex (XPC), the new CMOS-based system can be coupled with other 2200 Series systems.