DEC readies 225/275MHz Alphas

Electronic News, Oct 18, 1993 by Reinhardt Krause

MAYNARD, MASS.--Digital Equipment Corp. this week will announce 225 and 275 MHz versions of its Alpha AXP microprocessors--the first members in the family to be manufactured using a 0.5 micron, 3.3-volt, four-layer metal CMOS process. The 21064A-225 is expected to sample in December, priced at $877 in 5,000-unit quantities, while the 21064A-275 will sample in March, 1994, priced at $1,442 in similar quantities. Volume production at DEC's fabs in Hudson, Mass. and Scotland is set for late next year.

The new Alpha MPUs, pin-compatible with the existing 21064 family, are packaged in a 431-pin PGA. DEC said the 21064A-225--with 450 Mips peak performance, and the 21064A-275, estimated at 550 Mips peak operation--can be dropped in system designs built around the earlier Alphas. Just how fast the migration to the new parts will be remains to be seen; DEC's 200MHz 21064 is currently priced at about $1,300 in 1,000-unit quantitites. Although few users of the 200MHz parts have surfaced thus far, DEC said two will be disclosed at Comdex.

Dec also recently spun out two new Alpha MPUs--one incorporating the Peripheral Component Interconnect (PCI) local bus on-chip to target $3,000-range PCs running Microsoft's Windows NT and another positioned as a highend embedded version (EN, Sept. 13). At the same time, it reduce pricing on the 150MHz 21064 to $455 in 5,000-unit quantities.

Kevin Fielding, Alpha marketing manager, said he expected the new 225 and 275MHz Alpha chips to initially target high-end servers as the earlier MPUs continue to migrate down in pricing. He said the new Alpha versions were another step in DEC's strategy of pushing clock rates to hike performance, similar to Hewlett-Packard's and Mips Technologies' attempts to push their RISC architectures, and different in philosophy from IBM, Sun Microsystems and Intel. While DEC's benchmarks show the new Alphas topping other MPUs, he conceded, given their scheduled availability for sometime next year, that the competition was a moving target. The PowerPC 620, for example, is due out next year.

Despite the current lack of many top-name users for the Alpha--with the exception of Cray Research, Olivetti and Taiwan's Elite Group--Mr. Fielding said he felt the Alpha architecture would be able to compete against emerging PowerPC derivatives and Intel's Pentium. While IBM/Motorola/Apple PowerPC alliance is planning to support at least seven operating systems, Mr. Fielding claimed that strategy would confuse customers. He said DEC would continue its big bet on Windows NT for the desktop and OSF Unix and VMS for high-end systems. At Comdex, though, the PowerPC alliance is expected to make its own Windows NT announcement.

Mr. Fielding declined comment when asked if DEC's newest Alphs would satisfy Cray Research, which more than once recently has said it is not committed to DEC's RISC architecture for its second-generation massively parrallel processing systems (EN, Sept. 27).

The new MPUs use essentially the same micro-architecture, with on-chip cache doubled to 16K. Next-generation Alphas featuring a four instruction per cycle architecture will not debut until next year. The new process shrink, though, results in a 1.6 cm square die with 2.8 million transistors; power dissipation is about 80 percent of the previous 21064 devices.

Like earlier designs, the chips are designed for system logic running at 33MHz. To take advantage of the new part's speed, however, DEC is sticking with its plan of having system designers use off-the-shelf SRAM. It believes specialized SRAM caches such as a Motorola-developed solution for HP's PA7100 RISC architecture would be too expensive to attract the likes of Taiwan motherboard makers.