LSI's 3.3V ASICs debut via new 0.5-micron process

Electronic News, Nov 15, 1993 by Jim DeTar

MILPITAS, CALIF.--LSI Logic this week will introduce a new 3.3V, 0.5-micron ASIC process technology supporting its 500K product family--available as they array-based LCA500K, the embedded array LEA500K, and cell-based LCB500K implementations.

In moving from its 0.6-mircon, 5V technology to its next-generation process, LSI Logic is targeting both low-power system-on-a-chip applications, such as personal digital assistants (PDAs) and wireless communications. In addition, the 500K family addresses the performance requirements of telecom and EDP system designers by supporting interconnects as fast as 622MHz and system clock speeds in excess of 200MHz.

Accordingly, the prodcut family offers up to five pad pitch options and a choice of two-layer, three-layer and four-layer metal interconnect, depending on whether designs are core-limited or require embedded memory. The LCA500K offers up to 1.5 million available gates, with 1 million usable gates and 160Kbits of RAM; the LCB500K has the same density and 2MB of RAM; and the LEA500K embedded array offers similar density but faster prototype turnaround time.

The new ASIC family arrives just as LSI Logic is broadening its stragetic initiatives: targeting the asynchronous transfer mode (ATM) networking market with its ATMizer megacore (EN, Nov. 1), and leveraging its experience as a silicon partner for Apple Computer's PDA (EN, March 29).

"We are taking the ASIC business into the next gerneration," said Brian L. Halla, executive VP, LSI Logic Products Group. "We are redefining the semiconductor industry to a certain extend. Just about any system can be reduced to a single die. A television set-top decoder box, for example, will soon have on-command video and voice and the ability to access the data highway."

The new process will only be implemented at the company's Japan manufacturing complex, where production of newer products was shifted last year when LSI sold its Braunschweig. Germany site (EN, Aug. 31, 1992). Although competitors such as SGS-Thomson and IBM are moving to 0.5-micron ASIC technology as well industry analysts said LSI is differentiating its offerings, largely due to its process.

Dan Hutcheson, president of VLSI Research, said, "What I found unqiue is that it is probably the most complete ASIC solution you can find out there in terms of test and design capabilities and integration scale." Referring to LSI's hierarchical two-layer, three-layer and four-layer metal process options, he said, "What is impressive is that they did three-layer metal without CMP (chemical mechanical polisher)."

Jerry Worchel, senior ASIC analysts at In-Sat, said, "it (the 500K) is really a unique product in the sense that others have 0.5-micron technology with gate arrays but it's been based off of DRAM--not the most optimized techology you can have. Most of those products are limited in designed size. LSI designed it for ASICs, allowing optimized process and layouts."

LSI Logic's interconnect structure is constructed of TiN clad ALCu alloy, thick dieletrics and plugged vias that are in contrast to thinner dielectric and conductive layers in DRAM-based processes. The company said that the increasing use of metal layer technology is one reason for its different approach.

The LCA500K macrocells are based on a new basic cell architecture which reduces cells size by 10 percent. In addition, the 500K family includes a high- density three-transistor memory cell for densities of up to 2NB on chip. With a channel length of 0.35 micron, the process technology relies on sub-100A gate oxide and salicided transistors to reduce resistances.

System designers can also mix 3.3V and 2.4V functions on a single 500K die using LSI's hierarchical design metholodology and CoreWare libraries, said Mr. Halla.

"Process technology is a core competency and our market strategy sits on top of that. The 500K crashed through the threshold to put an entire solution on a chip. The equivalent to 1.5 million gates is 10 SPARC motherboards," he noted. "LSI has about 18 learning cycles a year, compared with the SIA average of 2 or 3 for most companies."

LSI is initially targeting four markets with the 500K: general telecom, communications transmission, digital video and systems logic. The 500K features pseudo ECL (PECL) drivers at speeds up to 622MHz, the target frequency for next-generation SONET telecom systems. It will also be marketed into emerging protocols such as ATM networks, which will initially be implemented at 155MHz.

Meanwhile, LSI's 500K test solutions include automatic Scan and JTA insertion, with automatic Boundary Scan Description Language (BSDL) generation. Packaging options vary from multiple high-pin count, fine-pad-pitch packages in Ball Grid Array (700 pins), quad flatpack and Chip-On-Tape technologies.

Samples of the 500K are available now; Mr. Halla said process qualification and limited production are expected by the second half of 1994, with volume production expected by the end of that year. NRE charges start at $30,000.