LSI Logic extends reach with CoreWare libraries

Electronic News, Jan 31, 1994 by Jim DeTar

MILPITAS, CALIF.--In a bid to extend its library of applications-specific integrated circuits (ASICs) deeper into the communications and mass storage markets, LSI Logic today plans to roll out three new CoreWare Library elements. All three are immediately available for ASIC designs using LSI's 0.6 micron, LCB300K cell-based process.

LSI's SeriaLink, Fibre Channel and SCSI-2 cores will round out the company's portfolio of products targeted at computer systems interconnect applications. The company said the products were designed for ease of portability to future processes. LSI intends to migrate to a 0.5 micron 500,000-gate process technology sometime in 1994.

The three additions to LSI's CoreWare Library are optimized to work in conjunction with its recently introduced CW33300 MIPS Core (EN, Nov. 5, 1993) that provides embedded intelligence for high-speed interconnect applications, such as gigabit-per-second host adapters and high-capacity storage controllers.

The three new products are also in line with LSI's declared strategy of providing technology that enables system-on-a-chip ASIC solutions for vertical markets, according to Kaushal Mehta, SeriaLink product manager.

Referring to a directive from Wilf Corrigan, LSI's chairman and CEO, Mr. Mehta noted, "We don't want to be perceived as a sea-of-gates vendor."

The SeriaLink core is a protocol-independent communications channel for interfacing with gigabit-speed physical media. LSI claims it is the industry's first gigabit-speed serial interface solution available as a CMOS core. It is seen as a replacement for GaAs or BiCMOS multi-chip interfaces, which typically cost more than the single-chip LSI SeriaLink.

The SeriaLink is a 600mW, data deserializer/serializer circuit that interfaces between an industry standard protocol and a physical media--fiber- optic or copper. The deserializer circuit receives a gigabit-speed serial data stream and converts it into parallel data suitable for any high-speed protocol handler.

The serializer reverses this process for output data. This is accomplished in a synchronous manner, keeping all control signals under a single clock domain. The core includes a clock recovery circuit to control input data rates and on-chip synthesizer (PLL) to generate the serial data bit clock for output data.

LSI's Fibre Channel core is thought to be among the first implementations of the recently finalized ANSI Fibre Channel Standard (FCS), a serial communications protocol supporting transfer rates of 100MB/sec. over distances up to 6.2 miles. Since it is bidirectional, the effective transfer rate can be 200MB/sec.

FCS provides mapping to SCSI and higher-level protocols such as FDDI and ATM, and is designed for scalable performance, from the current 100MB/sec. to terabyte/sec. speeds.

LSI's Fibre Channel core implements features of layers 1 and 2 of FCS. It supports class 1, class 2 and Intermix, as well as the Arbitrated Loop mode operation incorporated in the most recent revision of FCS.

The SCSI-2 core supports data transfer rates up to 10MB/sec. and is compliant with the ANSI standard for this protocol. Typical emerging storage applications include medical imaging and 100- to 500-channel video servers. LSI estimates that speeds of 755Mbits/sec. are required to provide live video to the desktop.

Another application driving high-speed I/O is mass storage redundant array of independent disks (RAID) products. A RAID with five Fast SCSI-2 drives running at 10MB/sec. per drive would create a front-end requirement of 50 MB/sec. Market research firm Disk/Trend estimates worldwide shipments of RAID systems will grow from $5.2 billion in 1994 to $7.9 billion the next year and $9.9 billion by 1996.

"Typical I/O solutions cannot keep pace with CPU speeds, creating a systems performance bottleneck," said Tom Harrington, CoreWare product marketing manager. "This is driving the development of new high-speed interconnect standards for all classes of computer systems.

"We looked closely at how these standards work together, and implemented them as part of our CoreWare products program. We also developed a critical additional piece, the SeriaLink core, to address the need for a protocol-independent connection to high-speed transmission media."

All three cores are immediately available for ASIC designs. Pricing of the cores is dependent on the level of customization, system building blocks used and manufacturing volumes. CoreWare Program fees begin at $25,000 and non-recurring engineering (NRE) charges start at $30,000.