Latest Altera design tool backs Windows NT, VHDL

Electronic News, Jan 31, 1994

SAN JOSE, CALIF.--With the release of MAX PLUS II version 4.0 this week, Altera will shift to a fully 32-bit software environment and establish itself as a programmable logic vendor supporting Microsoft's Windows NT operating system.

Altera said MAX PLUS II--its unified programmable logic development tool for the design, compilation and verification of Altera programmable logic devices--now incorporates the VHDL very-high-speed integrated circuit hardware description language synthesis. With the release of MAX PLUS II version 4.0, designers using IEEE standard VHDL-1076 can describe their circuits in VHDL for Altera devices.

In recent months, the popular VHDL standard got a boost when 11 companies banded together to form Analog VHDL International (AVI), an industry group targeted at helping along development of the IEEE 1076.1 standard--the analog extension of VHDL (EN, Sept. 20, 1993).

MAX PLUS II 4.0 was created using Microsoft's WIN32s software development kit. This allowed a 32-bit implementation of the software to run under Windows 3.1 or Windows NT. Altera said it will upgrade all existing MAX PLUS II users that hold maintenance agreements to the 32-bit version of MAX PLUS II free of charge. Support for Digital Equipment Corp.'s Alpha AXP workstation was also introduced, running under OSF/1.

Altera said it developed a VHDL module for MAX PLUS II that employs architecture-specific synthesis algorithms directly from VHDL constructs, resulting in increased silicon efficiency.

For example, "addition" operations described in VHDL are synthesized into Altera's SRAM-based FLEX 8000 family using FLEX's carry-look-ahead feature while the implementation into Altera's EEpROM-based MAX 7000 will utilize the family's logic expander capability.

VHDL-based design entry and synthesis are available on PCs and UNIX-based workstations. Altera has added VHDL synthesis support as an integrated part of the MAX PLUS II development system. Users may perform behavioral-level simulation and debugging using any third-party VHDL simulator, then pass the synthesizable VHDL constructs to MAX PLUS II.

"The adoption of VHDL is driven by the user community," said Don Faria, Altera's director of tools marketing. "Given the current advances in programmable logic, users of high-density devices are requiring the same top-down design capability as gate array and standard cell designers."

For PLD designers wishing to learn VHDL, the VHDL synthesis software comes with the IEEE 1076 Reference Manual, the textbook VHDL by Douglas Perry, an Altera VHDL user guide and on-line help.

In addition, with version 4.0, Altera also enhanced its interfaces to other CAE tools. Altera has added timing and area information to the MAX 7000 and FLEX 8000 synthesis libraries that support Synopsys' Design Compiler and FPGA Compiler products. In addition, MAX PLUS II version 4.0 software is now able to read and write OrCAD schematic files, complementing its other existing CAE interfaces.

MAX PLUS II version 4.0 is available now; and will be a free upgrade to all existing MAX PLUS II users under a maintenance agreement. VHDL synthesis support (PLSM-VHDL) is not included in the upgrade, but may be purchased for $3,995. UNIX versions of VHDL Synthesis (PLSM-VHDLWS) are available for $6,995 for Sun, HP and DEC platforms.

Altera this week also will reveal the latest round of certified results from the Programmable Logic Performance Corp. (PREP) industry standard benchmarks.

Results from PREP, an independent industry consortium of 13 providers of PLDs and PLD software tools, rated Altera's high-density FLEX 8000 family EPF81188-2 device at 42 benchmark instances ABC (average benchmark capacity), the largest certified programmable logic device rated by PREP.

Altera's MAX 7000 EPM7064-7 PLD scored well in the speed category, with an ABC (average benchmark speed) of 84MHz, 20 percent faster than any competing programmable logic device. The company also offers a wide range of products in between the high-density and high-speed benchmarks.

"PREP provides the first and only level playing field where the density and speed of all programmable logic devices can be compared in an 'apples-to-apples' format," noted Erik Cleage, Altera's vice president of marketing.