1994 Ad

Electronic News, Feb 21, 1994 by Jim DeTar

SAN FRANCISCO--Two Japanese companies made a splash with MPEG-2 technologies here last week at the International Solid-State Circuits Conference (ISSCC), with Matsushita claiming to have developed the first device capable of both encoding and decoding MPEG-2-based video data.

Toshiba, meanwhile, described a single-chip Motion Picture Expert Group (MPEG)-2 video decoder chip manufactured using a 0.5 micron triple-level aluminum CMOS process that allows a small 15x15mm square die size.

Thus far, U.S. and European companies have dominated the MPEG area, including the likes of C-Cube Microsystems, SGS-Thomson, Motorola, LSI Logic, IBM, AT&T and others. However, with the MPEG-2 standard now firmly in place, several Japanese companies are making a big push into MPEG devices. In addition, Taiwan's Winbond is also expected to soon enter the fray.

Matsushita's video digital signal processor (VDSP2) encodes and decodes MPEG-2 in real time by changing programs on the same chip. The VDSP2, packaged in a 261-pin ceramic PGA, integrates four different types of processors using 3.3V, 0.5 micron CMOS technology in an architecture that can operate them in parallel.

The VDSP2 features a DSP core; a variable length coding/decoding processor and a discrete cosine transform (DCT) processor. The DSP core consists of one programmable control unit and four vector-processing units. The VDSP2 includes a DRAM port, FIFO port, parallel port and video input port.

The device uses two-level parallel processing; the basic architecture consists of a macroblock (MB)-level pipeline and single-instruction multiple-data-stream (SIMD) vector pipeline. The device employs two encoding modes and a decoding mode. The MPEG-2 encoder, the most challenging feature, is implemented with two VDSP2 chips in different modes.

The FDSP2 is expected to be used in authoring equipment, Matsushita said, as well as in cable television systems, digital video discs, image database systems and multimedia devices that use the MPEG-2 standard for encoding and decoding.

The Matsushita device measures 18.6x16.7mm square and incorporates 2.5 million transistors. All instructions execute in a 10ns cycle, so the VDSP2 has 200Mips performance, the company said. Power consumption is 4.2 watts.

Toshiba's device decodes MPEG-2 standard bit streams. An on-chip RISC macro calculates actual motion vectors and addresses.

Toshiba's 3.3V single-chip MPEG-2 decoder features 1.1 million transistors, including 150,000 random logic transistors. ClocN frequency in CCIR601 format is 40MHz, and in HDTV format it is 70MHz. It is packaged in a 299-pin PGA.

There are three problems in MPEG-2 decoder design according to Toshiba. First, there is a memory bandwidth bottleneck from external DRAMs. Second, high-speed processing is needed due to computation-hungry MPEG-2 decoding. Third, the number of external DRAMs should be low to reduce system cost.

Toshiba said it first addressed the memory bandwidth bottleneck. The rate buffer, the reference picture buffer and display buffer are located in external DRAM in a mixed way. This reduces the number of DRAMs and the number of pins. This, combined with a bus arbitration unit that overcomes bus limitation issues, provides an improvement on the DRAM interface.

In order to achieve high-speed processing, Toshiba utilizes parallel operation of the VLD (variable length decoder) and the RISC. A hand-crafted VLD macro has an auto-decoding mode besides normal decoding modes. The VLD can decode a certain-length bit stream without aid of the RISC macro. This process is said to enhance chip performance by a factor of two, and achieves decoding of the HDTV with distribution quality bit streams.

Third, a data structure improvement to handle interlaced pictures that did not exist in MPEG-1. Additional features include use of embedded arrays, hand-crafted macros for memories, an IDCT (inverse discrete cosine transform) unit and the VLD unit for cost-effective implementation. Random logic provides a gate-array approach. "This approach provides the easy, fast customization needed for this consumer LSI," Toshiba said.

Toshiba also discussed 200MHz video compression macrocells using low-power swing differential logic at ISSCC.

"Improving the performance of fully dedicated macrocells is key to realizing HDTV-resolution video de/compression LSIs operating at more than 100MHz," Toshiba said, "having reasonable power consumption and chip size small enough for consumer applications.