Silicon Graphics airs Mips route into multimedia

Electronic News, April 11, 1994 by Reinhardt Krause

MOUNTAIN VIEW, CALIF.-- Silicon Graphics, Inc.'s move into consumer electronics markets such as Nintendo game machines and set-top terminals will be boosted by an upcoming "Mips Multimedia Architecture" that targets the integration of MPEG calculations such as discrete cosine transform (DCT) on-chip.

Forest Baskett, SGI's chief technology officer, and SGI's Mips Technologies subsidiary last week described the multimedia roadmap as well as other microprocessors such as the next-generation T5 and supercomputer-oriented TFP (EN, Feb. 21).

General-purpose MPU vendors targeting real-time video and emerging multimedia applications are starting to incorporate architectural extensions to manipulate graphics, image and video pixels as well as textual data; adding the instructions may eliminate the need for decoder chips or other devices. HewlettPackard's superscalar PA7100LC (EN, Dec. 20, 1993) is one noteworthy example.

"Our goals are more comprehensive and ambitious than HP's, but maybe that's my warped perspective," Mr. Baskett said. One of the driving forces in the evolution of sions of the TFP processor as welL the Mips architecture--besides higher-performance floating point for the technical computer market--will be reducing costs through greater integration.

"That's a force that pushes the architecture toward assuming more and more functionality that otherwise might appear in a graphics subsystem or in a decompression chip or in some voice processing circuitry or in an imaging subsystem," added Mr. Baskett. "What we call the Mips Multimedia Architecture, a target for a future generation of the Mips architecture, does do some of this incorporation of functionality for the multimedia world, into a new processor that has more functionality than you might expect from a simple RISC perspective. One of the things you want to be able to do in the multimedia world is to be able to do discrete cosine transfers. There are a variety of architectural enhancements that you can make that permit you to do discrete cosine transfers more easily and effectively with a given amount of sfiicon."

Some spins of the Mips architecture, most likely the R4200, are also likely to include the Rambus high-speed memory bus interface on-chip as a way to improve performance. But by targeting trigometric DCT calculations, a major component of the MPEG compression/decompression standard, Silicon Graphics is also stalking other's compression technologies such as P.64-based videoconferencing and JPEG.

With its PA-RISC 7100LC, HP's approach was to add extensions by implementing parallel halfword operations, said Larry Inman, HP program manager for advanced technology marketing. Those new instructions add, shift and multiply pixel data. The 7100LC also features dual integer ALUs. HP said an 80MHz 7100LC, now in its workstations and servers, can decode MPEG-1 audio and video at 25 frames/sec. at 352 x 288 resolution.

LSI Logic, meanwhile, includes some DCT algorithms in its compression devices that are designed into X-terminals. Andy Keane, Mips Technologies manager of microprocessor product marketing, said, "LS1 has a graphics chip that has fairly simple 2D-oriented instructions. Those extensions are not applicable to the 3D applications which would be more of Silicon Graphics' bent."

However, Mr. Keane indicated there are still unresolved architectural issues. "There is considerable discussion and review because it is a difficult problem. There may be a coprocessor extension (in the Mips architecture) but it's not a main instruction set extension. You don't necessarily need to add that to the instruction set of the machine. It can be in a coprocessor or it can be in a loosely coupled coprocessor," he said. The Mips architecture already includes coprocessing for memory management and floating point; one area is still open, however.

"What HP did and prior to that what the 88110 did for Motorola was they tried to find the most common, most basic graphics primitives and use those," Mr. Keane said. "That made a lot of sense because you are always manipulating pixels at a base level. But you may want to process on top more globally and that is the next level that people are looking at... the risk with any architectural extension is that you capture a broad number of applications and that those applications are going to live throughout the life of the architecture."

SGI has several multimedia projects under way, including its "Project Reality" program with Nintendo for 64-bit game machines (EN, Aug. 30, 1993); set-top boxes and video servers for Time Warner's interactive cable TV system in Orlando, Fla. (EN, June 14, 1993); and desktop systems such as the Indy workstation (EN, July 19, 1993).

A highly integrated device for Nintendo has been targeted for 1997. Silicon Graphics has also previously announced plans to incorporate ATM functionality into its settop boxes for Time Warner.

Mr. Keane added the DCT would map to an algorithm. "The way graphics work in an Indy and the way graphics work in a Reality engine are quite different. So they could potentially map to different types of graphics extensions."