National unveils new clock generators

Electronic News, April 11, 1994

SANTA CLARA, CALIF,--National Semiconductor revealed that a new family of clock generators it is currently rolling out is the primary clocking device used in Apple Computer's recently-introduced, PowerPC-based Power Macintosh (EN, March 14).

In addition to being used with the PowerPC architecture in the Power Mac, all three members of National's new CGS clock generator family--the CGS700V, CGS701V and CGS410V--pare currently available for general sampling and are applicable to a variety of RISC and CISC MPUs, according to National.

"As overall computing system speeds increase, internal clock synchronization between functions becomes imperative. National's CGS product offerings address (these) system timing demands," said Anthony Ochoa, National's senior technical marketing engineer.

Mr. Ochoa said that National's CGS family of clock generators was designed with the loads of the PowerPC-based Power Macs in mind, but has a generic architecture that can be used with any RISC or CISC processor. KIt can actually be described as an application specific standard product that has a generic architecture," Mr. Ochoa said. "It can be used in the Apple PowerPC systems but we are also getting inquiries on Pentlure systems and even for some RISC processors for Hewlett-Packard."

The CGS700V is the primary clock generator for the PowerPC 601 RISC-based Power Mac, while the CGS701V is a related clock generator with added external feedback, i.e., the 701V differs from the 700V in that it has an external feedback loop that can be used to provide "zero delay" during synchronization. The third new IC, the CGS410V, is used by Apple to provide clocking for a variety of monitor sizes and configurations.

Said to be off-the-shelf clock drivers, the 700V and 701V provide low skew outputs which are produced at different frequencies from three fixed input references. The XTALIN input pin is designed to be driven from three distinct crystal oscillators running at 25MHz, 33MHz or 40MHz. All of the CGS circuits are based on phase-lock loop (PLL) technology that controls the signals within the device. Both the 700V and 701V can output docks as fast as 160 MHz.

Regarding clock generator accuracy, period-to-period jitter in the 700V/701V is guaranteed at 40 picoseconds (ps), while pin-to-pin skew is guaranteed at 500 ps. "Characterization data from our lab tests of the 700V and 701V, however, show considerably better performance," asserted Bernard Ta, clock generator product manager. "Qualification testing over temperature and voltage showed long term jitter at a maximum of only 260 picoseconds, while skew was measured at 275 picoseconds under the same conditions."

The devices feature an output buffer of nine drivers, 25MHz to 160MHz output frequency range, outputs operating at 4X, 2X, 1X of the reference frequency for multi-frequency bus applications and selectable output frequency.

The 410V, meanwhile, can be used to drive a variety of graphic display monitors and can also be used on add-in monitor accelerator cards. It features user-programmability so that designers can program to various dot clock frequencies to meet the needs of differing screen resolutions and refresh rates.

Additional features include programmable frequency generator, frequencies up to 135 MHz, confignrable high-speed complementary CMOS clock outputs, single 5-volt operation, low power dissipation of 500mW, automatic clock de-glitching function, read/write control register and internal VCO and loop filters. National admitted, however, that the CGS410V is sensitive to noise on certain pins, especially FREQCTL, Filter, AVDD and AGND, so special care must be taken with board layout for optimum performance. All three circuits are packaged in 28pin PLCC packages. The CGS700V and 701V are priced at $10 each in lots of 100 and are expected to be in quantity production by May. The CGS410V is available in quantity now; priced at $13.30 each in lots of 100.

National also is expected today to take the wraps off what is thought to be the first 22V10 programmable logic device (PLD) that incorporates IEEE 1149.1 boundary-scan technology on the 22V10 architecture National first introduced and currently licenses to other companies such as Cypress Semiconductor.

National's SCAN22CV10 is designed to reduce board cost and system level testing by extending boundary-scan test to densely-populated circuit board designs.

Compliant with the IEEE 1149.1 JTAG standard, the SEAN22CV10 is a standard 22V10 PLD architecture with hardwired boundary scan support. This configuration enables designers to utilize industry standard tools and existing JEDEC files to migrate existing PAL/GAL designs to the new scan devices.

"Since the 22V10 is one of the most common means of eliminating glue logic, this device brings new SCAN testing to a large number of previously unscannable devices," said Dave Lewis, National's 22V10 product marketing manager.

National's SCAN22CV10 emulates 24-pin PAL and GAL devices. It uses four "no connect" pins of the PAL and GAL22VlO in PLCC to implement the four scan signals: test data in (TDI), test data out (TDO), test clock (TCK) and test mode select (TMS). The SOIC pin out also maintains pin and programmer compatibility with standard 22V10s, so designers can use available programming hardware and software tools. National said it guarantees a minimum of 100 erase/write cycles.