Synopsys unveils verification tools suite

Electronic News, Sept 19, 1994

BEAVERTON, ORE. - The Logic Modeling Group of Synopsys is introducing PLdebug, a suite of design and system verification tools for field programmable gate arrays (FPGAs) and complex programmable logic device (CPLDs). PLdebug is an option to Logic Modeling's SmartModel Library, which contains programmable device models from all leading vendors.

PLdebug is available now as a $5,900 option to SmartModel Library. That is the pricing for North America.

The software uses Logic Modeling's new SmartCircuit technology for modeling FPGAs and CPLDs. "Even designers who use simulation to verify their CPLD- and FPGA-based designs are encountering a new set of problems as high-level design methods obscure the details of the original design through synthesis, routing and other processing," said David Hardman, director of marketing for SmartModel products at Logic Modeling. "The SmartCircuit technology and the design tools it supports reflect a significant commitment to providing design verification tools that anticipate advances in programmable device complexity and the increasingly sophisticated capabilities of simulation and synthesis tools."

SmartCircuit's features, incorporated into PLdebug, include Casual Tracing SmartCircuit Monitor and SmartBrowser. Casual Tracing allows the designer to locate the root cause of any logic event, trace the effects of any logic event and identify the cause of timing constraint violations, according to Logic Modeling. Without casual tracing, designers may need to analyze manually hundreds of possible logic paths over the course of a design to locate the true source of problems.

SmartCircuit Monitor lets the user probe internal states and signal elements inside the CPLD or FPGA during simulation, Logic Modeling said. Users can specify particular instances, nets and ports to be monitored during the simulation run. SmartCircuit Monitor reports state changes over time, which is useful for tracing state machine execution.

SmartBrowser is an interactive netlist browser that allows the designer to navigate through an unfamiliar post-route design. Users can traverse up and down the logic hierarchy, traverse forward and backward from any point and place traces and monitor points. The software also allows users to view cell timing and modify it to evaluate effects during simulation.

Various FPGA and PLD vendors offered testimonials to the usefulness of PLdebug. "The SmartCircuit technology and the new PLdebug tools demonstrate Logic Modeling's continuing commitment to work with its partners in the semiconductor industry to make easier for users to make the most productive use of FPGAs in their applications," said Gervais Fong, CAE relations manager at Actel.