Stable PLL designs raise performance

Electronic News, Sept 26, 1994 by Andy Santoni

SANTA CLARA, CALIF.--TriQuint Semiconductor used a self-contained phase-locked loop (PLL) clock generator design and a 0.7-micron gallium arsenide (GaAs) process to develop its recently-introduced Fibre Channel transmitters and receivers that offer a high level of integration, a range of frequencies, high performance and low cost (EN, Aug. 8 1994). The transmit devices perform parallel-to-serial conversion and generate the internal high-speed clock for the serial output; the receiver recovers the clock and data from the serial data stream, provides byte alignment, and performs serial-to-parallel conversion.

The devices "interface to other vendors' Fibre Channel controllers or to TriQuint's upcoming encoder/decoder (ENDEC) chip. The transmitter/receiver chipset and a fiber optic module set provide all the functionality of the Fibre Channel's FC0 and FC1 layers, and partial support for the FC2 layer, he said. Applications include high-speed computer networking, disk drive and storage subsystem interconnection, mainframe channel communications, and point-to-point proprietary links.

The latest devices from TriQuint, as reported, are the FC1063 and FC531 Fibre Channel transmit/receive chipsets. These operate at the Fibre Channel's highest specified rate, 1,063Mbps and at half-speed (531Mbps), respectively. The firm also offers the FC266, a quarter-speed device. This makes TriQuint one of the few companies to offer chipsets that perform Fibre Channel FC0 functions at all three speeds, said Sunil Sanghavi, director of marketing for TriQuint's Computer and Networking division.

According to Mr. Sanghavi, the FC1063 and FC531 offer the highest performance in the industry, with jitter at 75 picoseconds (ps) maximum and power at 2.25 watts (W) typical. TriQuint's on-chip PLL design is responsible for the low jitter, which enhances data integrity and reduces hard error count, thereby improving bit error rate (BER) performance, explained Mr. Sanghavi. The devices run from single 5-volt (V) power supplies and operate over the entire 0 to 70 C temperature range without space-, cost-, and power-consuming cooling devices, he noted. The low power consumption and single power supply operation reduce system power budgets and improve reliability, he added.

The transmitter and receiver in each chipset is packaged in a 44-lead MQUAD package. This small, low pin count package requires less board space than competing devices, which typically are offered in 64-pin or larger packages, according to Mr. Sanghavi. It also simplifies layout and reduces cost, he noted.

Price starts at $56 for the FC531 and $73 for the FC1063 in 1,000 quantities, and Jason Knickerbocker, senior product marketing engineer at TriQuint's Computing and Networking Division, claimed the FC1063 is priced more than 20 percent below the nearest competitive device.

Mr. Knickerbocker credited a stable, reproducible design for high manufacturing yields and therefore low price. At the heart of the design is the PLL clock generator.

While some competitive devices require an external filter capacitor for the PLL, TriQuint integrates the filter capacitor, explained Mr. Knickerbocker. "A significant portion of TriQuint's die is the filter capacitor for the PLL," he said. "This obviously increases die size, but we feel it is absolutely mandatory to minimize noise injection into the sensitive PLL circuitry. Using an external capacitor exposes the guts of the PLL to the noisy outside world."

An FC531 or FC1063 transmitter serializes a 10-bit transistor-transistor logic (TTL) input into a differential pseudo emitter-coupled logic (PECL) output. The device is composed of an input register, a parallel-to-serial converter, the PLL clock generator, a differential output buffer, and a PECL-to-TTL translator (Figure 1). The input data (TXD0 to TXD9) is latched into the input register on the rising edge of the TXCLK clock signal. The parallel-to-serial converter serializes the data into a differential PECL buffer. TXD9 is sent first and TXD0 is sent last.

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The loop enable (LOOPEN) pin selects between the two differential output pairs, TLX and TLY or TX and TY. The differential PECL-to-TTL translator is normally used to translate PECL signals generated by optical receiver to TTL signals to drive control circuitry. An FC531 or FC1063 receiver consists of a clock and data recovery circuit, a multiplexer, and a serial-to-parallel converter block (Figure 2). The multiplexer selects between the RX and RY inputs or the RLX and RLY inputs. The multiplexer output is selected by the LOOPEN pin. The selected data goes to the clock/data recovery (CDR) block.

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The CDR block has two modes: clock recovery and frequency acquisition. In the clock recovery mode, the CDR recovers the clock signal from the input serial data. If there is no data at the CDR serial input, it automatically switches to the frequency acquisition mode, which causes the CDR to lock onto the reference clock (REFCLK) signal. This prevents the PLL from drifting away from the serial data rate and ensures that the CDR will properly lock onto the input serial data when it is reapplied.