Sun sets SuperSPARC-II as UltraSPARC V9 bridge

Electronic News, Oct 10, 1994 by Jim DeTar

SUNNYVALE, CALIF.--Sun Microsystems SPARC Technology Business (STB) unit will today roll out what will likely be the final member of the SuperSPARC RISC (reduced instruction set computer) architecture series--the SuperSPARC-II microprocessor family with clock speeds of 75MHz and 90MHz. Designed as a bridge technology for Sun customers as they transition to the new UltraSPARC V9 architecture (EN, June 27), SuperSPARC-II features up to a 50 percent increase in clock frequency over the original SuperSPARC, which tops out at 60 MHz.

Sun will also today unveil an upgraded version of the current MXCC cache controller, dubbed the MXCC II External Cache Controller, and reveal plans to cut the price of existing SuperSPARC processors when the SuperSPARC-IIs begin to ship in 1Q95.

Sun, which claims an installed base of more than 150,000 multiprocessing-capable systems, is trying to capture an even larger share of the desktop multiprocessing system market with SuperSPARC-II, according to Peter von Clemm, STB product marketing manager. Sun says there is an inherent parallel nature to much of the work environment for today's computer user. For instance, an EDA engineer needs to work on refining a design while running a complex circuit simultation at the same time; or managers in a large corporation might want electronic conferencing between two different sites, requiring realtime video along with a shared electronic whiteboard for illustrating different points.

"SuperSPARC pioneered multiprocessing on the desktop. It was streamlined to provide multiprocessing and multithreading and the (SunSoft WorkShop suite) tools came into play allowing for a wide range of different uses," Mr. von Clemm noted in an interview with Electronic News. Whereas SuperSPARC could accommodate up to two processors in a multiprocessor system, SuperSPARC-II allows for up to four chips in one desktop system, up to 20 processors in a server, and up to 64 processors in supercomputers such as the Cray series, which utilizes Sun MPUs. The new SuperSPARC-II is also plug compatible with all previous SuperSPARC chips.

Sun continues to evolve both hardware and software in order to provide a multiprocessor solution, according to Fuad Abunofal, STB design project manager. "Solaris 2.4 is excellent for utilizing multiprocessing systems. On top of that, there are hooks in the library that will let the customer utilize the multiprocessing system. And we are seeing more and more multithreaded applications. We have new compilers from SunSoft and applications ISVs (independent software vendors) can write applications to utilize that." SuperSPARC-II supports both MBus and XBus multiprocessing systems, and is binary compatible with the approximately 9,400 existing applications developed for previous SPARC processors.

However, as Sun's UltraSPARC chips ramp production, they will supplant SuperSPARC-II--and there will probably be no SuperSPARC-III, according to Mr. von Clemm. Sun will, however, continue to support SuperSPARC OEMs with higher performance versions in the near-term.

"We have no plans to do any significant market architecture work to it, although you will likely see increased performance. But in terms of a (transition to a) new design, like the one from SuperSPARC-I to SuperSPARC-II, that's not likely. We want to push technology and performance but not at the expense of our customers. The 75 and 90MHz will initially meet their needs. You may see another version with higher speed than 90 MHz next year. But the adoption rate for new technology on UltraSPARC is such that, within a year of shipping, we will get a pretty complete transition by our customer base to using that. Eventually that (UltraSPARC) becomes more costeffective and, during the transition period, you want to offer them a choice."

The 3.1 million transistor SuperSPARC-II MPU was designed on a 0.8-micron, three-layer metal BiCMOS process. "Our major goal was to improve the cycle time," Mr. Abunofal noted. "We looked at SuperSPARC for bottlenecks and we found several areas where we could improve sppeed." In order to remove these speed bottlenecks, Sun attempted to balance the pipeline by compressing decode phases, which allows more time for the execution stage. It also simplified the internal timing to single-edge design. In addition, the company added register file and TLB (Transistor Look Ahead buffer), upgraded the on-chip floating point unit (FPU) by doubling the precision adder array and the precision multiplier array, and changed the I/O buffers to 90MHz to match the new processor's higher internal clock speed.

SuperSPARC-II features include a 17.2x17.5mm die size, 19 watts power consumption and three-way superscalar performance that yields an estimated 115 SPECint92 and 125 SPECfp92 benchmark performance for the 75MHz version, and 135 SPECint92 and 147 SPECfp92 for the 90MHz chip. The original SuperSPARC offers 1.5 SPECint per MHz, and SuperSPARC-II also measures 1.5 SPECint per MHz performance while at the same time running at up to 50 percent faster.