First new product emerges from Alta Group

Electronic News, Oct 31, 1994

FOSTER CITY, CALIF.--Alta Group introduced HDS 3.0, a new release of its Hardware Design System with enhancements to bridge the gap between concept and implementation of electronic systems. The new version generates design descriptions in the Verilog hardware description language (HDL), in addition to VHDL, from a graphical design specification, and features an HDL Import capability and HDL co-simulation through a link between Alta's system-level simulator and leading HDL simulators.

Pricing for HDS 3.0 begins at $10,000 (node-locked) for Alta's existing SPW customers. Pricing for non-SPW customers starts at $35,000. The software operates on Sun Sparc platforms running SunOS and Solaris, Hewlett-Packard workstations, the IBM RISC System/6000 and Digital Equipment Corp. Alpha workstations. It will be available in Q4 on the Sun platforms.

This is the first new product to come out of Alta since Redwood Design Automation was merged into the Cadence Design Systems unit (EN, Design Software, Sept. 19). HDS was originally introduced in 1991, and it is said to offer a transition between the system design phase and the IC design, enabling users to capture and verify a hardware architecture within the same design environment that was employed to capture the system's behavior. Target applications include wireless communications, networking and multimedia systems.

"HDS has always provided designers with powerful VHDL generation capabilities and links to synthesis for top-down design," said Baruch Deutsch, product marketing manager for hardware design tools at Alta. "Now, with the addition of Verilog HDL and co-simulation support to HDS, Alta becomes the first company to offer an application-specific, production-proven path from conceptual design to physical implementation combining a top-down and bottom-up methodology."

HDS 3.0 provides users with a choice between VHDL or Verilog as their target language, according to Alta. Verilog can be generated from a signal flow or behavioral block diagram, similar to the way VHDL is generated today. The generated HDL code is at the registertransfer level and can be simulated on a Verilog simulator and can be synthesized by such tools as VHDL Compiler and HDL Compiler from Synopsys and Synergy from Cadence.

The HDL Import capability supports both top-down and bottom-up design flows. In top-down design flows, HDL users can manually create HDL code for certain blocks in their design specification. In a bottom-up design flow, HDL users can incorporate existing HDL description within a newly created block diagram. In both cases, users are able to co-simulate HDS blocks with HDL code in a unified verification environment. This is accomplished with links to popular HDL simulators, such as Cadence's Leapfrog and Verilog-XL and Synopsys' VHDL System Simulator (VSS).

HDS 3.0 also provides an update to its Signal Calculator feature that now includes a new "logic analyzer" display mode. Under this mode, users can mix system-level signals such as noise, speech or video with lower-level logic signals, such as bits or words. With this feature, Signal Calculator provides users with a mixed-level (system to gates), mixed-mode (analog-digital) display and analysis tool.

Additional enhancements include a new set of hardware architecture blocks for use by designers in capturing complex system descriptions. Bringing the number of library elements from approximately 60 to more than 100 elements, the new high-level blocks now available with HDS 3.0 include such functions as shift registers, FIFOs, stacks, dual-port RAMs, ALUs, multiply accumulators and encoder/decoders.