The EDA design flow for ASIC gate arrays

Electronic News, Nov 14, 1994 by Rita Glover

The diagram on the following two pages has been created to illustrate the extensive scope of electronic design automation (EDA) processes and tools. To limit the wide scope of EDA tools, it was decided to summarize the design flow and tools that are available for creating gate-array application specific integrated circuits (ASICs). This diagram does not include the process and tools for designing user-programmable logic devices, because they differ quite significantly from the paradigm for masked gate arrays. This diagram also does not attempt to deal with board-level systems, such as printed circuit boards, multichip modules and hybrids.

The basic methodology for the electronic design of masked ASICs may be thought of as having two parallel paths: an implementation path and a verification path. These two paths are traversed in parallel during the design process, and the tools must interface with each other in a common computer environment.

The implementation process is fed by libraries that contain data on components, simulation models and predesigned modules. These libraries may be supplied by a vendor or developed by the user.

The design environment is important to the success of the process. A design environment is usually provided by an EDA vendor's framework, into which tools of choice can be made to "plug and play," but it also may be user-developed at advanced sites. System-level design is facilitated when tools of choice from more than one supplier are able to be operated within a common design environment.

Design entry entails the creation of data describing the ASIC's input/outputs (I/Os) and functionality. Design entry tools allow input and editing in many different graphical and textual formats, and usually different parts of the design may be described in different formats, depending on the user's preference. Early verification is performed at this stage with appropriate tools for the type of design entry that was done.

The main part of the ASIC design process consists of transforming the design description, however it was entered, into an implementation of gates and signals. With today's complex chips, this can only be accomplished through the technological miracle of logic synthesis, a process during which many highly specialized optimizations and algorithms are applied to achieve area and timing constraints. As synthesis tools have evolved, users have gained more and more ability to control the synthesis process and affect the resulting implementation. During synthesis, the optional addition of manufacturing test features is becoming widely used by those who recognize the value of designing for testability. Various verification steps are again performed at this stage, and results are compared to earlier verification runs.

The final stage of ASIC implementation is physical layout of the silicon mask. This phase is often passed off to the semiconductor manufacturer for implementation, since it is often process-specific. Designers of custom chips do perform these steps, however, and they use special tools for cell design, floor planning, partitioning, placement and routing. Many specialized verification tools are required to assure the reliability of the physical design, and this need increases as chips reach submicron geometries.