Compass, Synopsys will integrate planning software

Electronic News, Dec 12, 1994

SAN JOSE, CALIF. - Compass Design Automation will work with Synopsys to tie its floorplanning and place-and-route tools with Synopsys' synthesis offerings. Targeting deep-submicron designs, the new interface technology from Compass is expected to be available in 2Q95.

"We currently have a solid design flow between Synopsys' synthesis tool and Compass' floorplanning tool, and have seen tremendous success with hundreds of customer designs,- said Steve Kompolt, product marketing manager at Compass. As leader in our respective fields, this link has been critical for today's deep-submicron designs. Looking forward, we believe at a tightly integrated design flow between Synopsys and Compass will be beneficial as our customers continue to move to finer process geometries.

Mr. Kompolt added that Compass can make use of data in such standard formats as the electronic design interchange format EDIF) and the standard delay format (SDF), allowing outputs from synthesis software marketed by Cadence Design Systems, Mentor Graphics and Viewlogic Systems, among others. Whose synthesis people want to use isn't an issue with us,- he said.

"Synopsys is pleased to have Compass; support for Floorplan Manager,- said Nitin Deo, product line manager for links to layout at the Mountain View, Calif.-based Synopsys. "We will work with Compass to validate the interface to our synthesis tools. ChipPlanner software customers can now have tighter MM with Synopsys synthesis tools to improve accuracy and time to market for deep-submicron devices."

Compass noted that ChipPlanner is supported by a number of ASIC suppliers and foundries besides VLSI Technology, Compass' parent company. They include Mitsubishi, Hyundai, Goldstar, Taiwan Semiconductor Manufacturing Co. (TSMC), Hitachi, American Microsystems, Inc. (AMI), MHS and the latest addition to the roster, Toshiba (EN, Antenna, Nov. 28). Compass reported that Metsubishi and AMI now offer design kits that will allow their ASIC customers to use Compass' ASIC Navigator design environment and the ChipPlanner floorplanning tool.

Compass has also revealed several new enhancements for ChipPlanner. Users of the floorplanning tool now have access to timing-driven, path-oriented placement embedded in a floorplanner. The new placement algorithms adhere to the path throughout the placement phase, including estimated and final placement, and meeting timing constraints set by Synopsys' Design Compiler software. ChipPlanner can also optimize a design's clock tree during floorplanning and as part of the logic synthesis loop, reducing clock skew in the design.

As part of the tighter links between Compass and Synopsys software, users can now synthesize designs using Design Compiler and then output the data in an EDIF Me to Chip-Planner. ChipPlanner then automatically generates a floorplan and can accurately model the interconnect delay between circuit elements at each stage of design iteration, according to Compass. Customers can eliminate all timing violations using Synopsys' In-Place Optimization capabilities and Compass' engineering change order (ECO) capability to update the floorplan. The ChipPlanner tool can then pass the optimized design to routers supporting the LEF and DEF format, with exact correlation to the floorplanned design.