Synopsys branches out

Electronic News, Feb 13, 1995 by Jeff Dorsch

MOUNTAIN VIEW, CALIF.--Synopsys is branching out from its traditional base in synthesis with the introduction of a line of tools for designing at the source level of hardware description languages (HDLs).

The company last week unveiled DesignSource and HDL Advisor, the first two packages in the Source-level Design line (EN, Antenna, Feb. 6). Synopsys executives emphasized these products will form the foundation for a broader product line, with more capabilities to come.

"There is a fundamental shift occurring," said, Aart de Geus, president and CEO of Synopsys, at last week's press conference. "We're moving toward functionality, captured in language."

He drew an analogy between the introduction of these products and the impact of source-level software development tools on programmers more than a decade ago. Once Fortran and C language compilers became available and highly reliable, it was no longer necessary for software developers to work in assembly code.

The same leap in productivity and efficiency could be achieved with these packages and their successors, according to Synopsys. "A lot of people are doing iterations at the back end, just catching small problems with their source code," said Paul Estrada, director of marketing at Synopsys. With Source-Level Design, designers can iterate directly on their source, in Verilog HDL or VHDL, before simulation and synthesis, to avoid time-consuming and expensive iterations at the end of the design process.

"The concept of source-level tools makes a lot of sense," said Steve Edlefsen, member of the technical staff at TRW in El Segundo, Calif., an alpha customer for the new Synopsys tools. "If I could do design iterations before simulation and synthesis, I would definitely design faster and get better results. Based on what I've seen so far, I'm excited about the potential of this new technology."

Gary Smith, senior analyst at Dataquest, said: "The move to source-level design will have as significant an impact on the hardware world as it had in software. Designers basically want to see as much information as possible, as early as possible. Since the source is what they created and understand most intuitively, designing at the source will deliver immediate productivity gains."

DesignSource and HDL Advisor are priced together at $34,000 in the U.S. HDL Advisor is individually priced at $24,000 and will be available in 2Q95. DesignSource is individually priced at $17,000 and available in 3Q95.

DesignSource is a fullsource capture tool, capturing and manipulating various inputs throughout the design process. Designers can enter and edit designs using two graphical editors that directly reflect Verilog and VHDL structure, according to Synopsys. The Hierarchy Editor provides graphical control of operations such as design linking and swapping alternative architectures. The structural Block Editor is optimized for entering design objects (structures) and connectivity.

DesignSource also captures the associated design information. Scripts and test-benches are bound and tracked directly in the Hierarchy Editor. Generics, attributes and parameters are set and stored on structural objects. Because of the close links with Synopsys' other design tools, DesignSource can drive design tasks directly from the source--packaging and controlling associated data, launching synthesis and simulation and automatically tracking the results.

HDL Advisor is a sourcelevel analysis tool that includes two real-time analysis engines. Prior to simulation or synthesis, the HDL Analysis engine directly analyzes the implicit logic structure of the source to show connectivity, levels of logic, generic component count and the component fan in/fan out, Synopsys said. After synthesis, the Performance Correlation engine relates technology-mapped timing, area, capacitance and power analysis back onto the HDL at registers and hierarchical boundaries.

Designers can view the analysis information in a number of dynamic, cross-referenced views for fast problem solving. The Histogram and Profiler windows show the distribution and relative contribution of performance across the design for quickly locating "hot spots" and bottlenecks. The HDL Browser shows annotated text for relating design performance directly to the Verilog and VHDL source. The Path Browser is a source-and gate-level path analyzer for exploring connectivity and tracing paths. Designers can see the Boolean expression for any point in their design.

John Cooley of the E-mail Synopsys Users Group called these products "a significant change" for Synopsys. "They've thought out what they've done, rather than plunging into it. It's not a `me too' product, like Test Compiler, but a quasi-novel approach to design entry, and speeding up that."

He was especially impressed by HDL Advisor, which he said is "a good analysis tool for experienced guys, and it helps new guys learn the ramifications of their actions." In HDL Advisor, Synopsys is "selling experience for writing HDL from a synthesis point of view."