Lattice Semiconductor will triple CPLD offerings

Electronic News, Feb 13, 1995 by Jim DeTar

HILLSBORO, ORE.--Lattice Semiconductor will today triple the size of its complex programmable logic device (CPLD) portfolio with the launch of the 2000 series and 3000 series of ispLSI/pLSI families aimed at PLD market volume leaders Altera and Xilinx.

The new 2000 series includes a high-density device that Lattice claims is the industry's fastest high density CPLD--the 154Mhz, 5.5-nanosecond ispLSI/pLSI 2032-150-and the 3000 series offers what Lattice is touting as the industry's largest [E.sup.2]CMOS CPLD to-date--the 11,000-gate ispLSI/pLSI 3256.

However, the first member of the 2000 family to ship, the 32-macrocell ispLSI/pLSI 2032, is currently available in 80-, 110-, 135- and 150MHz versions. In addition, 64-, 96-and 128 macrocell members of the family are slated to be introduced by mid-year.

A successor to the 1000 CPLD family, the 3000 family extends from 2,000 to 8,000 gates. The initial ispLSI/pLSI 3256 offering contains 256 programmable generic logic blocks (GLBs) and is available in 50- and 70ns speed grades, with system operating frequencies of 77Mhz and 57Mhz and logic delays (Tpd) of 15ns and 20ns, respectively. An 8,000-gate device, the 192-macrocell ispLSI/pLSI 3192, is scheduled to be available next quarter, and a 14,000-gate CPLD, the 320-macrocell 3320, is expected to be in production in the second half of this year.

In the three product families: series 1000, 2000 and 3000, there will be a total of 20 device options.

The company also revealed initial customers for the new ispLSI/pLSI 2000 and 3000 families, including Fibermux for selected versions of the devices in its network hubs; Qualcomm for integration of the devices into its next generation wireless telephone systems; and Coreco for video capture boards.

Stan Kopec, Lattice's director of marketing, commented in an interview with Electronic News that "This new generation of CPLDs has highdensity PLDs that match today's higher performance processors--a milestone for Lattice." He said although high-density PLDs account for only 22 percent of the company's business, "Lattice's business will continue to transition to the high-density market and, two years from now, high density products will probably be a majority of our business. Low density will continue to grow as well--our objective is to have a full spectrum of devices."

Mr. Kopec also revealed that Lattice is nearing release of its first product implemented on 0.5-micron process. "Half-micron will be our next technology--we will move to 0.5-micron this year, within the next six months hopefully." Although the company advanced $42 million to its manufacturing partner, Seiko Epson, last year to help Seiko convert its sub-micron fab about 200 miles north of Tokyo in Sakata, Japan (EN, May 23, 1994), Lattice has no plans currently to add to that investment. "We don't foresee any incremental investment in Seiko Epson this year."

In addition to 384 registers and 128 universal I/O pins, the ispLSI/pLSI 3256 CPLDs also have five dedicated clock input pins, and proprietary technology features, including Lattice's Output Routing Pool (ORP) to enable OEMS to maintain pinouts, and Global Routing Pool (GRP) to provide inter-connectivity between all device elements. Dedicated Boundary Scan registers and test control logic compliant to the IEEE 1149.1 standard is also a standard feature of the 3256. Device outputs have independent

programmable output slew rate control which provides adjustable signal switching speed on each pin in order to minimize overall electro-magnetic interference (EMI) and system noise.

In addition, the ispLSI 3256 can be programmed or reprogrammed on the system printed circuit board due to the 5-Volt In-System Programmable (ISP) technology. Lattice counts among its customers Northern Telecom Ltd., which cites the company's ISP technology as a factor in its decision to partner with the company. "Northern Telecom is currently pursuing isp on our designs due to our recognition of the cost advantages that may be obtained by removing handling steps from the manufacturing flow," said John Chiang, senior component engineer, Northern Telecom.

Besides ISP, the cost savings enabled by reduced part counts was cited by another Lattice customer, NEC America. "NEC America appreciates the benefits that ispLSI offers to manufacturing, such as reduced part types and flexible inventory," stated Brian Reilly, senior hardware development engineer.

The 2000 series, meanwhile, offers a lower gate count (1,000- to 6,000) but higher number of I/Os (up to 128) than the existing 1000 and new 3000 families. Spearheading the family is the 154Mhz, 5.5ns ISPLSI/pLSI 2032-150 which offers input signal set-up time (Tsu) of 3ns and clock-to-output time (Tco) of 4.5ns. By delivering this set of specs, the company said, the ispLSI and pLSI 2032 provide a performance match with microprocessors operating at speeds up to 75Mhz.

"The most significant aspect of this second generation of the ispLSI and pLSI 2032 devices is how we optimized the timing for operation with fast microprocessors such as the Pentium," Mr. Kopec said. "We studied the processor bus requirements and minimized setup time to 3ns to allow fast address strobing and decoding."