Galileo has cache controller for IDT's MPU designs

Electronic News, Feb 13, 1995

SAN JOSE, Calif.--Galileo Technology has introduced a stand-alone secondary cache controller for the Integrated Device Technology IDD R4600 and R4700 high-end 64-bit RISC microprocessors; the company claimed it is the only such device strictly for the IDT part.

The GT-64012 uses a zero wait-state mechanism for accessing data that does not fit in the CPU's primary cache, and that would otherwise need to be fetched from slow DRAM-based main memory. Performance improvements are code and system dependent, but have been measured in the 20 percent to 100 percent range in the system evaluations conducted so far, Gauleo said.

"We are extremely pleased to have committed the GT-64012 program 64012 many months ago, in anticipation of the R4600 family's increased popularity," said Gallieo president Manuel Alba. "We'll take integration and performance a step further with our upcoming single-chip PCI System Controller for the R4600 and R4700."

The architecture of the GT-64012 is 64012 designed to enable the addition of a secondary cache to an existing system without changes to the system ASICs or controller logic, resulting in a cost-effective increase in performance. It is essentially a "transparent' controller, with write-through, direct mapped, 32-byte line size attributes.

The cache controller is designed with 5-Volt BiCMOS technology and supports up to 50MHZ clock speeds in the bus with no walt-states, which means that it supports the R4600/R4700-100MHz in up to divide-by-2 mode; the R4600/R4700-133MHz and R4600/R4700-150MHz in up to divide-by-3 mode; and the R4700-175MHz in up to divide-by-4 mode.

The GT-64012 supports industry-standard synchronous burst SRAMs typically used with Intel processors, in an attempt to take advantage of the economies of scale associated with the PC industry. By supporting synchronous SRAMs, zero wait-state is attained without the need for interleaving, thus reducing component count, board space and loading while improving granularity, according to Galileo.

Either two or four data SRAMs are needed to build a 256KB or 512KB cache. At the maximum bus speed of 50MHz, the GT-64012 requires the 12 nanosecond version of the SRAMs.

In addition, the new device is designed to work with defacto standard IDT cache tags, which are fast SRAMs that include the tag comparison logic on-chip, ensuring no wait-state operation. Furthermore, an external QuickSwitch from Quality Semiconductor allows the 5V GT-64012 to work at full speed in 3.3V systems.

Separately, an evaluation product, dubbed the Galileo-2 module, is available along with a reference design. The Galileo-2 module consists of a small PC board that is plugged into an existing R4600 or R4700 179-PGA socket, replacing the CPU. The CPU is then plugged into a similar 179-PGA socket on the Galileo-2 module.

The module contains the GT-64012 secondary cache controller, a 16Kx15 tag SRAM, four 32Kx18 or 64Kx18 burst SRAMs, and 4 standard logic components. Designers can alternately use two of the newer 32Kx36 burst SRAMs for the smaller cache configuration.

The GT-64012 is sampling packaged in a 44-pin PLCC and priced at $22.50 each in 10,000-unit quantities. The Galileo-2 evaluation module and its reference design are currently available for shipment, priced at $995 without CPU and with 512KB of cache.