Hitachi buoys synchronous memory

Electronic News, March 13, 1995

BRISBANE, CALIF.--Steering the mainstream memory market toward synchronous memory designs, Hitachi America separately rolled out a 1-Mbit synch burst static RAM (SRAM) and a 4-Mbit synch DRAM aiming to bolster performance in cache memory and graphics solutions, respectively.

The 32Kx32 HM62C3232 SRAM now being sampled by Hitachi offers pipelined operation as a cache solution for mid-range desktops and portable PCs which can do without the 20 percent premium associated with faster flow-through parts, such as the company's recently-introduced HM67B3632, said Narayan Purohit, Hitachi's product marketing manager for SRAM and non-volatile products.

"This part is going to be the mainstream second-level cache for the Pentium market," Mr. Purohit said. "We expect it to be a very high volume part. We think that in 1995, the 32 by 32 will be an allocated device." He added that industry-wide demand is expected to outpace supply for the part by 20 percent for the better part of the year.

The 3.3-Volt HM62C3232--made in a CMOS 0.5-micron process-supports Pentium burst sequence and provides I/O registers for address, data and control pins. Access speed options are 8-, 9-, 10- and 12 nanoseconds, allowing clock speeds up to 66Mhz. Mr. Purohit said the 66Mhz market will snap up 8ns versions while slower 50MHz systems will need 12ns versions.

Other features include 15ns cycle times, industry-standard LVTTL I/O, internal self-timed write cycle, plus internal address, data and control input registers to off-load the CPU bus and boost system performance.

With the 32Kx32 organization, system designers have a choice between a two-chip 256KByte solution and a four-chip 512KByte second-level cache, though Mr. Purohit acknowledged most customers will choose the two-chip design because of the capacity constraints. Sampling now, the 8ns version of the HM62C3232 device in a 100-pin QFP package is $25 in 10,000-piece quantities.

On another front, Hitachi is moving headlong into synch DRAMS with the 3.3V, 4-Mbit device having an 80MHz clock speed. The HM5241605TT-12 offers 166MBytes per second bandwidth, making it comparable in performance with dual-ported memory devices while supporting integrated DAC/graphics controllers, said Jim Sogas, product manager for application specific memories. "For graphic controller chips, all you have to do is turn up the clock and you get that much more bandwidth. This is going to be the workhorse of the graphics memory market."

The device can be configured as a two-chip, 1MByte solution with a 32-bit wide interface which Mr. Sogas said is considered the minimum frame buffer requirement for 1,024x768 resolution displays. The chip features a 12ns cycle time, various Iffl-page burst lengths, sequential and interleaved bursts, pulse RAS, hidden precharge and both auto- and self-refresh. The part is being fabricated using 0.8-micron CMOS technology, a process Mr. Sogas said is "cheap and easy to get."

Samples for the HM5241605TT-12 are available now for $17.95 in 1,000-piece quantities. Volume production is scheduled to begin 2Q95. Its 66MHz, 4-Mbit predecessor sells for about $16 each in volume quantities.