Costello: we need one design language

Electronic News, April 3, 1995 by Jeff Dorsch

SANTA CLARA, Calif. - Cadence Design Systems president Joseph Costello last week renewed his call for the industry to adopt a single design language, one that would incorporate elements of the incompatible VHDL and Verilog languages.

Giving the keynote address at the annual International Verilog Conference (IVC), Mr. Costello said the industry adoption of VHDL was "one of the biggest mistakes in design automation history," and it has caused both users and electronic design automation vendors to waste hundreds of millions of dollars in bridging the language gap.

The increase of VHDL usage was initially "not driven by users," Mr. Costello said. "This was a 'push' event, not a `pull' event. A bunch of EDA vendors decided to make this a differentiator."

Mr. Costello was apparently referring to the 1991 formation of VHDL International, an industry organization founded to promote usage of VHDL, a documentation language originally developed for the Department of Defense's Very High Speed IC (VHSIC) program. EDA vendors dominated the membership rolls of the organization in the beginning, but Cadence was pointedly excluded from the founding of the group. It later joined VHDL International.

It was nearly three years ago, at the VHDL International Users Forum spring meeting in Scottsdale, Ariz., that Mr. Costello first decried the costliness of having the semiconductor industry support two incompatible design languages (EN, May 15, 1992). At the time, VHDL seemed to be ascendant, and some VHDL proponents were boldly predicting that Verilog would be "dead" in three years.

What has happened is that it's a bilingual industry, with VHDL still increasing in usage and Verilog enjoying a robust existence, on its way to becoming an IEEE standard, as VHDL is.

Verilog was originally created by Gateway Design Automation, acquired by Cadence in 1989. The following year, Cadence put the design language in the public domain and created Open Verilog International (OVI) for stewardship of the language. That move created a small industry of companies making Verilog "clone" simulators and other products for using Verilog.

Although VHDL predated Verilog by about a year, it did not become widely used in ASIC design until the late 1980s. The contention by some observers that "VHDL forced Verilog to open up" isn't true, Mr. Costello said last week. "Cadence talked about opening up Verilog before the Gateway acquisition."

In passing, Mr. Costello said there were discussions in the late '80s about a three-way merger among Cadence, Gateway and Synopsys - a combination which would have created a simulation and synthesis powerhouse today.

Intel's experience with its embarrassing floating-point calculation bug in the Pentium points out that there are serious flaws in the current top-down design methodology of simulation and synthesis, Mr. Costello said. "I believe we are starting to run out of steam with our design methodology," he stated. "We've got to do something else."

The design flow of the future needs to take a "golden model" as its center, according to the Cadence CEO. "What feeds that golden model? Not VHDL or Verilog," he said. "We need to have a different language."

The new language should be "some kind of extension of existing languages," Mr. Costello said, and it should be a true hardware description language (HDL). Verilog is not actually an HDL, as it is frequently characterized, but a simulation language, he added.

Having to support two different design languages has been "extremely costly" for both users and vendors, Mr. Costello said. "It would be better if we were solving problems real customers have."

Mahendra Jain, executive director of VHDL International, agreed that it would be advantageous if the industry had only one design language to support, but the state of things is that Verilog and VHDL "will co-exist," he said.

"People will buy what they want," he added. "The customer will decide what's best for him."

On the subject of unifying design languages, Mr. Jain said "People have looked at it," but added it is not clear how it could be achieved. Some new tools make it unnecessary for users to get involved in generating HDL code, he noted. "Customers can be shielded from HDLs."

As Mr. Costello observed, last week's IVC could have been called a "co-simulation conference," as there were at least three leading products exhibited that promise to run Verilog and VHDL simulations together without the use of a simulator backplane.

Bill Fuchs, chairman of OVI, last week reported the results of a survey of revenues by OVI members. With about 90 percent of the membership responding, 1994 revenues of Verilog software products were estimated at $272 million, including $121.8 million in sales of Verilog simulators, he said. That compared with 1993 revenues of about $170 million.

'I think Verilog's on a roll, growing far greater than expected," he said. Reports by market analysts that VHDL has overtaken Verilog in industry usage are incorrect, he added.

He also said that balloting on the proposed IEEE 1364 standard, which would make Verilog an official standard, is expected to begin within the next month. There are about 300 voters. Three-quarters of those voters must return their ballots and 75 percent of those votes must be in favor for the standard to succeed. The result should be clear by September, at the latest, he estimated.