AMD's RISC Am29000 expansion leads embedded systems session

Electronic News, April 10, 1995 by Jim DeTar

ATLANTA--RISC embedded microprocessors and the Peripheral Component Interconnect (PCI) local bus will be spotlighted here at the third annual Embedded Systems Conference East, April 18-20 at the Inforum. Included in a broad spectrum of companies planning to introduce products at the conference is Advanced Micro Devices (AMD), which will expand its RISC-based Am29000 family with a mid-level addition targeting printers and other cost-sensitive systems.

Another embedded RISC competitor, Integrated Device Technology (IDT), will introduce a new family of 3.3-Volt MPUs for handheld devices and other embedded applications, as well as a now suite of software tools to assist embedded designers, while Intel, Digital Equipment Corp. and Hewlett-Packard all plan product introductions at the conference.

The convergence of PCI with Motorola's 68000 processor in embedded systems platforms will be highlighted as Motorola and Newbridge Microsystems disclose a strategic relationship. They have created an interface device dubbed Spanner, which they will also unveil at the conference, designed to adapt 68K designs for use with PCI components.

AMD's planned expansion of its flagship Am29K line will bring the number of 32-bit RISC MPU and MCU versions in the family to 12. The new offering is designed to deliver low-cost RISC performance and a high level of graphics. Its feature set is calculated to make it highly suitable for laser and inkjet printers, as well as industrial control and graphics applications.

The new chip will be positioned between AMD's Am29200 and Am29205, which currently are specified by Microsoft for Windows Printing System (WPS) reference designs. Existing 29K customers who would likely be potential customers for the new device include HP, Xerox and Toshiba, as well as Apple Computer and Compaq Computer.

One of the features of the new Am29k MCU is an IEEE-compliant parallel interface, an item the company included as it set its sights on the printer market. In addition, the embedded MCU will combine a variety of technical features to achieve high 16 VAX MIPS performance at 20MHz operating frequency, including fully pipelined three-address instruction architecture, 22-bit address bus, 192 general-purpose registers and a 104MB address space. Sources said the chip will also include glueless system interface to DRAM and ROM with on-chip wait state control and a two-channel DMA controller with queued reload for use in internal peripherals.

Motorola and Nowbridge will reveal production plans for the new Spanner interface, which will be billed as the first commercially- available PCI-to-68040 bridge. The first member of the PCI/68K family, the Spanner peripheral PCI/68K bridge, will soon be followed by a Spanner PCI/68K host bridge.

Newbridge outlined some of the technical issues Motorola 68K designers may encounter in attempting to create systems utilizing PCV68K bridges, and some of the solutions as well, in a white paper which says, in part: "For both the cost and architectural advantages of PCI, designers of embedded systems (where 68K dominates) will contemplate transplanting their 68K designs to PCI. However, various technical issues arise when you bridge PCI with 68K-type buses. For example, fundamental differences exist in addressing (notably endian issues), cycle protocols and interrupt management."

One suggested approach for bridging mismatched buses is a decoupled architecture where the operation of one bus is kept isolated from the operation of the other. Other solutions are suggested as well.

The paper also details the differences between the Spanner peripheral PCI/68K bridge and the Spanner host PCI/68K bridge. "There are two functionally distinct PCI/68K bridges. There is a host PCI/68K bridge which would require the following: flexible 68K slave image programming for configuration and control of various PCI peripherals, deep decoupling FIFOs, an integral DMA, an integral PCI bus arbiter and an integral interrupt controller. The peripheral PCI/68K bridge would differ from the host PCI/68K bridge in that it would provide simpler 68K slave image programming, optimize data throughput for transactions originating from a 68K initiator, and also not require the integrated functionality of the host bridge. All of this would make the peripheral PCI/68K bridge significantly less expensive then the host bridge."